[AMDGPU] Register assertion fails on select from address space

[jhuber6]

The code in https://godbolt.org/z/naaYMjh97 hits a backend assertion when built in assertions mode.

target triple = "amdgcn-amd-amdhsa"

define amdgpu_kernel void @_start(ptr %0) {
  %2 = select i1 false, ptr %0, ptr addrspacecast (ptr addrspace(5) null to ptr)
  %3 = getelementptr i8, ptr %2, i64 -1
  %4 = load i8, ptr %3, align 1
  %5 = icmp eq i8 %4, 0
  br label %6

6:
  br i1 %5, label %7, label %6

7:
  ret void
}

$ llc bug.bc -mcpu=gfx90a
llc: /root/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:370: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Joseph Huber (jhuber6)

The code in https://godbolt.org/z/naaYMjh97 hits a backend assertion when built in assertions mode. ```llvm target triple = "amdgcn-amd-amdhsa"

define amdgpu_kernel void @_start(ptr %0) {
%2 = select i1 false, ptr %0, ptr addrspacecast (ptr addrspace(5) null to ptr)
%3 = getelementptr i8, ptr %2, i64 -1
%4 = load i8, ptr %3, align 1
%5 = icmp eq i8 %4, 0
br label %6

6:
br i1 %5, label %7, label %6

7:
ret void
}

```console
$ llc bug.bc -mcpu=gfx90a
llc: /root/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:370: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.

[tgymnich]

(lldb) p BaseLoDef->dump()
  %21:vgpr_32, %22:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 -1, 0, 0, implicit $exec
(lldb) p BaseHiDff->dump()
  %24:vgpr_32, %25:sreg_32 = V_ADDC_U32_e64 -1, %18.sub1:sreg_64, killed %22:sreg_32_xm0_xexec, 0, implicit $exec

BaseLoDef has only imm operators because of gep ptr nullptr, i64 -1.

Adding isReg checks for BaseLo and BaseHi should be sufficient.