AMDGPU silently converts incorrect physical register asm constraint to virtual register

[arsenm]

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s

define void @invalid_sgpr(<2 x i32> inreg %arg0) {
  call void asm sideeffect "; use $0", "{s[1:2]}"(<2 x i32> %arg0)
  ret void
}

s[1:2] is not a valid SGPR reference as 64-bit SGPRs require even alignment. This is silently accepted, and appears to be treated as a virtual register constraint. In -stop-after=finalize-isel, I see:

    %10:sreg_64 = COPY %11
    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:SReg_64 */, %10

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

``` ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s

define void @invalid_sgpr(<2 x i32> inreg %arg0) {
call void asm sideeffect "; use $0", "{s[1:2]}"(<2 x i32> %arg0)
ret void
}

s[1:2] is not a valid SGPR reference as 64-bit SGPRs require even alignment. This is silently accepted, and appears to be treated as a virtual register constraint. In -stop-after=finalize-isel, I see:

%10:sreg_64 = COPY %11
INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3997705 /* reguse:SReg_64 */, %10

</details>

[ritter-x2a]

#123590 has a patch for this problem.