[MSP430][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (5/8)

[llvmbot]

Bugzilla Link	44042
Version	trunk
OS	All
Reporter	LLVM Bugzilla Contributor
CC	@rotateright

Extended Description

A number of comparisons involving bit tests are converted into shifts by InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit targets with comparatively cheaper selects.

It is desirable that selects are emitted instead of shifts for these targets. The following cases were identified in TargetLowering and DAGCombine and were fixed by:

https://reviews.llvm.org/D69116
https://reviews.llvm.org/D69120
https://reviews.llvm.org/D69326
https://reviews.llvm.org/D70042

Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that these cases should be fixed by reversing the current canonicalisation. I am showing them in this and following reports:

REPORTED CASE:

Source code:

int testShiftAnd_0more( int x )  // (InstCombineCasts:transformSExtICmp)
{
  return x<0 ? -1 : 0;
}

IR code:

define i16 @testShiftAnd_0more(i16 %x) {
entry:
  %x.lobit = ashr i16 %x, 15
  ret i16 %x.lobit
}

MSP430 Target code:

testShiftAnd_0more:
	swpb	r12
	sxt	r12
	rra	r12
	rra	r12
	rra	r12
	rra	r12
	rra	r12
	rra	r12
	rra	r12
	ret

AVR Target code:

testShiftAnd_0more:
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	asr	r25
	ror	r24
	ret

EXPECTED RESULT:

Source code:

int testShiftAnd_0more( int x )  // (InstCombineCasts:transformSExtICmp)
{
  return x<0 ? -1 : 0;
}

Expected IR code:

define i16 @testShiftAnd_0more(i16 %x) {
entry:
  %cmp = icmp slt i16 %x, 0
  %cond = sext i1 %cmp to i16
  ret i16 %cond
}

Expected MSP430 Target code:

testShiftAnd_0more:
	mov	r12, r13
	mov	#-1, r12
	tst	r13
	jl	.LBB4_2
	clr	r12
.LBB4_2:
	ret

Expected AVR Target code:

testShiftAnd_0more:
	tst	r25
	brmi	LBB4_2
	ldi	r24, 0
	ldi	r25, 0
	ret
LBB4_2:
	ldi	r24, 255
	ldi	r25, 255
	ret

[benshi001]

AVR has gained great optimization on 8/16/32-bit shifts.

[llvmbot]

@llvm/issue-subscribers-backend-msp430

[rotateright]

Almost the same as issue #43389 - this is very unlikely to change in IR:
https://godbolt.org/z/qqTch7oY9

[benshi001]

I am sure AVR has gained great improvement, https://godbolt.org/z/xbxPnfhjM
with your original source code

int testShiftAnd_0more( int x )  // (InstCombineCasts:transformSExtICmp)
{
  return x<0 ? -1 : 0;
}