Description
This is an umbrella ticket for the work on refining the assembler-related parts of the backend and common LLVM infrastructure. Includes elimination of workarounds, turning custom code into TableGen definitions, simplifications and fixing minor defects found during the work.
32f6b6b [AMDGPU][AsmParser] Refine parsing SDWA operands.
5114843 [AMDGPU][AsmParser] Refine SMRD offset definitions.
32f46ef [AMDGPU][AsmParser][NFC] Refine immediate operand definitions.
b06e5ad [AMDGPU][AsmParser][NFC] Simplify parsing cache policies.
905fa15 [AMDGPU][AsmParser] Distinguish literal and modifier SMEM offsets.
dbbab71 [AMDGPU][NFC] Eliminate the u32imm operand definition.
f0f8ae7 [AMDGPU][AsmParser] Fix matching immediate literals.
3d6b108 [AMDGPU] Remove the unused u8imm operand definition.
ce1aae4 [AMDGPU][AsmParser][NFC] Refine defining single-bit custom operands.
9976127 [AMDGPU][AsmParser][NFC] Refine defining i8- and i16-typed custom operands.
2d945ef [AMDGPU][NFC] Rename GFX10A16 operands.
0a6dc9a [AMDGPU][AsmParser] Refine parsing cache policy modifiers.
536b8c5 [AMDGPU][AsmParser] Remove the now-unused OptionalOperand structure.
fce7a7a [AMDGPU][AsmParser] Refine parsing instruction operands.
926acd2 (arcpatch-D137638) [AMDGPU][AsmParser] Remove extra checks on missing instruction modifiers.
af6b1f7 [AsmParser] Match mandatory operands following optional operands.