missed optimization for trunc i32 to i16 or i8 when ConstantRange of source already fits in destination

[MitalAshok]

An unnecessary zeroextend / signextend is emitted to zero bits that are already assumed to be zero.

For example:

void take_u16(std::uint16_t);
void u32_to_u16(std::uint32_t x) {
  __builtin_assume(std::in_range<std::uint16_t>(x));
  take_u16(x);
}

Emits an unnecessary movzwl %di, %edi before the tail call. GCC optimizes this to just jump to take_u16.

https://godbolt.org/z/qE77z3a7d

This optimization can also be done on other targets

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Mital Ashok (MitalAshok)

An unnecessary zeroextend / signextend is emitted to zero bits that are already assumed to be zero.

For example:

void take_u16(std::uint16_t);
void u32_to_u16(std::uint32_t x) {
  __builtin_assume(std::in_range<std::uint16_t>(x));
  take_u16(x);
}

Emits an unnecessary movzwl %di, %edi before the tail call. GCC optimizes this to just jump to take_u16.

https://godbolt.org/z/qE77z3a7d

This optimization can also be done on other targets

[pinskia]

Note GCC and LLVM implement 2 different ABIs for argument passing on x86_64 still. GCC optimizes this due to it following the upper bits of the registers is not defined and not even taken into account the __builtin_assume here.

[RKSimon]

declare void @llvm.assume(i1)
declare void @take_u16(i16 noundef zeroext) 

define void @u32_to_u16(i32 noundef %x) {
entry:
  %or.cond.i = icmp ult i32 %x, 65536
  tail call void @llvm.assume(i1 %or.cond.i)
  %conv1 = trunc i32 %x to i16
  tail call void @take_u16(i16 noundef zeroext %conv1) #3
  ret void
}

Unfortunately currently we can't insert an AssextZext node for t2:

Initial selection DAG: %bb.0 'u32_to_u16:entry'
SelectionDAG has 12 nodes:
  t0: ch,glue = EntryToken
  t4: i64 = GlobalAddress<ptr @take_u16> 0
        t2: i32,ch = CopyFromReg t0, Register:i32 %0
      t3: i16 = truncate t2
    t5: i32 = zero_extend t3
  t7: ch,glue = CopyToReg t0, Register:i32 $edi, t5
  t11: ch,glue = X86ISD::TC_RETURN t7, TargetGlobalAddress:i64<ptr @take_u16> 0 [TF=7], TargetConstant:i32<0>, Register:i32 $edi, RegisterMask:Untyped, t7:1

[RKSimon]

Many of these are now handled thanks to trunc nsw/nuw flags:

define dso_local void @u32_to_u16(i32 noundef %x) local_unnamed_addr {
entry:
  %cmp2.i = icmp ult i32 %x, 65536
  tail call void @llvm.assume(i1 %cmp2.i)
  %conv1 = trunc nuw i32 %x to i16
  tail call void @take_u16(i16 noundef zeroext %conv1) #3
  ret void
}

u32_to_u16:
        jmp     take_u16@PLT

[RKSimon]

Ignoring the i16 -> i8 cases (for now), these are the remaining failures (vs gcc):

i32_to_i8:
  movsbl %dil, %edi
  jmp take_i8@PLT

i32_to_u8:
  movzbl %dil, %edi
  jmp take_u8@PLT

i64_to_i8:
  movsbl %dil, %edi
  jmp take_i8@PLT

i64_to_u8:
  movzbl %dil, %edi
  jmp take_u8@PLT

i32_to_i16:
  movswl %di, %edi
  jmp take_i16@PLT

i32_to_u16:
  movzwl %di, %edi
  jmp take_u16@PLT

i64_to_i16:
  movswl %di, %edi
  jmp take_i16@PLT

i64_to_u16:
  movzwl %di, %edi
  jmp take_u16@PLT

[RKSimon]

At least some of the remaining issues appear to be due to a failure to recognise a split (extended) i128 integer

https://alive2.llvm.org/ce/z/RSe21U

----------------------------------------
define i1 @src(i32 noundef %x) {
entry:
  %coerce.sroa.0.0.extract.trunc = sext i32 noundef %x to i64
  %#0 = ashr i32 noundef %x, 31
  %coerce.sroa.2.0.extract.trunc = sext i32 %#0 to i64
  %x.sroa.2.0.insert.ext.i = zext i64 %coerce.sroa.2.0.extract.trunc to i128
  %x.sroa.2.0.insert.shift.i = shl nuw i128 %x.sroa.2.0.insert.ext.i, 64
  %x.sroa.0.0.insert.ext.i = zext i64 %coerce.sroa.0.0.extract.trunc to i128
  %x.sroa.0.0.insert.insert.i = or disjoint i128 %x.sroa.2.0.insert.shift.i, %x.sroa.0.0.insert.ext.i
  %r = icmp samesign ult i128 %x.sroa.0.0.insert.insert.i, 256
  ret i1 %r
}
=>
define i1 @tgt(i32 noundef %x) {
#0:
  %xx = sext i32 noundef %x to i128
  %r = icmp samesign ult i128 %xx, 256
  ret i1 %r
}
Transformation seems to be correct!