[DAG] Match some basic ISD::AVGCEILU patterns

[RKSimon]

Pulled out of Hacker's Delight, both of these are valid patterns that can be folded to ISD::AVGCEILU (assuming the target supports it):

define i4 @fixedwidth(i4 %a0, i4 %a1)  {
  %or = or i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = lshr i4 %xor, 1
  %res = sub i4 %or, %srl
  ret i4 %res
}
define i4 @zext_add_inc_extract(i4 %a0, i4 %a1)  {
  %x0 = zext i4 %a0 to i5
  %x1 = zext i4 %a1 to i5
  %sum = add i5 %x0, %x1
  %inc = add i5 %sum, 1 
  %srl = lshr i5 %inc, 1
  %res = trunc i5 %srl to i4
  ret i4 %res
}

Both aarch64 and x86 have some ISD::AVGCEILU vector support, so we can test this with either - x86 already has a rather messy detectAVGPattern function that I hope we can eventually get rid of and just have a regular DAG combine, so try to keep away from that for now :)

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

1. In the comments of the issue, request for it to be assigned to you.
2. Fix the issue locally.
3. Run the test suite locally. Remember that the subdirectories under test/ create fine-grained testing targets, so you can e.g. use make check-clang-ast to only run Clang's AST tests.
4. Create a Git commit.
5. Run git clang-format HEAD~1 to format your changes.
6. Open a pull request to the upstream repository on GitHub. Detailed instructions can be found in GitHub's documentation.

If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

Pulled out of Hacker's Delight, both of these are valid patterns that can be folded to ISD::AVGCEILU (assuming the target supports it):

define i4 @<!-- -->fixedwidth(i4 %a0, i4 %a1)  {
  %or = or i4 %a0, %a1
  %xor = xor i4 %a0, %a1
  %srl = lshr i4 %xor, 1
  %res = sub i4 %or, %srl
  ret i4 %res
}
define i4 @<!-- -->zext_add_inc_extract(i4 %a0, i4 %a1)  {
  %x0 = zext i4 %a0 to i5
  %x1 = zext i4 %a1 to i5
  %sum = add i5 %x0, %x1
  %inc = add i5 %sum, 1 
  %srl = lshr i5 %inc, 1
  %res = trunc i5 %srl to i4
  ret i4 %res
}

Both aarch64 and x86 have some ISD::AVGCEILU vector support, so we can test this with either - x86 already has a rather messy detectAVGPattern function that I hope we can eventually get rid of and just have a regular DAG combine, so try to keep away from that for now :)

[Sh0g0-1758]

I have expressed my interest in working on #84749. Since this is similar, I would like to work on this also.

[aniplcc]

Hi, this looks like a good way to get into DAG, would love to explore the codebase and work on this!