Regression in codegen for some SIMD operations

[jfalcou]

While checking for code generation quality of EVE, our SIMD wrapper, I encountered this issue between clang 15 and 18

https://godbolt.org/z/daxdhvbTx

After a short discussion on Discord, we ended up with those more streamlined repro:

Sources
Generated IR 1
Generated IR 2

[dzaima]

Those simplified repros only are inefficient on 18.1.0 but not trunk; here's IR that's inefficient on trunk, note the freeze, which, if removed, results in the better vmovmskps instead of packing+vpmovmskb.

IR

define noundef i32 @foo(<8 x float> noundef %x) {
foo.exit:
  %0 = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
  %1 = fcmp oeq <8 x float> %x, %0
  %2 = bitcast <8 x i1> %1 to i8
  %3 = zext i8 %2 to i32
  %.fr = freeze i32 %3
  ; %.fr = bitcast i32 %3 to i32
  %cmpz = icmp eq i32 %.fr, 0
  br i1 %cmpz, label %cond.end, label %cond.false

cond.false:                                       ; preds = %foo.exit
  %4 = tail call i32 @llvm.cttz.i32(i32 %.fr, i1 true)
  br label %cond.end

cond.end:                                         ; preds = %cond.false, %foo.exit
  %ctz = phi i32 [ 32, %foo.exit ], [ %4, %cond.false ]
  %5 = icmp eq i8 %2, 0
  %conv = select i1 %5, i32 undef, i32 %ctz
  ret i32 %conv
}

declare i32 @llvm.cttz.i32(i32, i1 immarg) #0

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

The assembly also expends effort to return a fixed 32 for a zero mask, even though that's explicitly undef, returned from a noundef function even. (fwiw, opt pipeline link of the original C++ on trunk)

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Joel Falcou (jfalcou)

While checking for code generation quality of EVE, our SIMD wrapper, I encountered this issue between clang 15 and 18

https://godbolt.org/z/daxdhvbTx

After a short discussion on Discord, we ended up with those more streamlined repro:

Sources
Generated IR 1
Generated IR 2

[RKSimon]

define i32 @PR90847(<8 x float> %x) {
entry:
  %shuf1 = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
  %min1 = tail call noundef <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %x, <8 x float> %shuf1)
  %shuf2 = shufflevector <8 x float> %min1, <8 x float> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5>
  %min2 = tail call noundef <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %min1, <8 x float> %shuf2)
  %shuf3 = shufflevector <8 x float> %min2, <8 x float> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
  %min3 = tail call noundef <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %min2, <8 x float> %shuf3)
  %fcmp = fcmp oeq <8 x float> %min3, %x
  %mask = bitcast <8 x i1> %fcmp to i8
  %zext = zext i8 %mask to i32
  %cmp = icmp eq i8 %mask, 0
  %tz = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %zext, i1 false)
  %conv = select i1 %cmp, i32 undef, i32 %tz
  ret i32 %conv
}

lllc -mattr=+avx2

PR90847:                                # @PR90847
        vshufps $177, %ymm0, %ymm0, %ymm1       # ymm1 = ymm0[1,0,3,2,5,4,7,6]
        vminps  %ymm1, %ymm0, %ymm1
        vshufpd $5, %ymm1, %ymm1, %ymm2         # ymm2 = ymm1[1,0,3,2]
        vminps  %ymm2, %ymm1, %ymm1
        vpermpd $78, %ymm1, %ymm2               # ymm2 = ymm1[2,3,0,1]
        vminps  %ymm2, %ymm1, %ymm1
        vcmpeqps        %ymm0, %ymm1, %ymm0
        vextractf128    $1, %ymm0, %xmm1
        vpackssdw       %xmm1, %xmm0, %xmm0
        vpacksswb       %xmm0, %xmm0, %xmm0
        vpmovmskb       %xmm0, %eax
        testb   %al, %al
        je      .LBB0_1
        movzbl  %al, %eax
        rep       bsfl        %eax, %eax
        vzeroupper
        retq
.LBB0_1:
        movl    $32, %eax
        vzeroupper
        retq

llc -mcpu=x86-64-v3

PR90847:                                # @PR90847
        vshufps $177, %ymm0, %ymm0, %ymm1       # ymm1 = ymm0[1,0,3,2,5,4,7,6]
        vminps  %ymm1, %ymm0, %ymm1
        vshufpd $5, %ymm1, %ymm1, %ymm2         # ymm2 = ymm1[1,0,3,2]
        vminps  %ymm2, %ymm1, %ymm1
        vpermpd $78, %ymm1, %ymm2               # ymm2 = ymm1[2,3,0,1]
        vminps  %ymm2, %ymm1, %ymm1
        vcmpeqps        %ymm0, %ymm1, %ymm0
        vmovmskps       %ymm0, %eax
        tzcntl  %eax, %eax
        vzeroupper
        retq

So technically this goes away as all AVX2 targets also have tzcnt - but there is still an underlying regression due to freeze insertion we should address.