Closed
Description
The Cortex M7 chip (ISA v7-EM) from ARM supports the "FPv5" floating point spec:
https://developer.arm.com/documentation/ddi0489/f/floating-point-unit/about-the-fpu
Just built llvm from release tag 18.1.7
and ran the following:
llvm-project/build/bin/llvm-tblgen --dump-json llvm-project/llvm/lib/Target/ARM/ARM.td -I=llvm-project/llvm/include -I=llvm-project/llvm/lib/Target/ARM > ARM_TARGETS.json
To verify which options were supported.
Floating point features for the Cortex M7 (and in general) only go up to vfp4
.
ARM chips are backwards compatible with previous floating point versions, so it's valid to use vfp4
for the Cortex-M7, however it caused me a good deal of confusion when porting a project from GCC to find vfp5
nowhere in sight!
For context this was discovered because:
- Zig uses
llvm-tblgen
to parse + populate some enums that define valid LLVM features per CPU - I am developing with Zig + a Cortex M7 based MCU, and was confused why
vfp5
wasn't in the available CPU features