Skip to content

Issues: llvm/llvm-project

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
154 Open 404 Closed
154 Open 404 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[MCP] Handle iterative simplification during forward copy prop llvm:globalisel llvm:regalloc
#140267 opened May 16, 2025 by preames Loading…
3
[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties debuginfo llvm:globalisel llvm:regalloc llvm:SelectionDAG SelectionDAGISel as well
#140002 opened May 15, 2025 by jurahul Loading…
2
[CodeGen][NPM] Port ProcessImplicitDefs to NPM backend:AMDGPU backend:X86 llvm:regalloc
#138829 opened May 7, 2025 by optimisan Loading…
3
[CodeGen][NPM] VirtRegRewriter: Set VirtReg flag llvm:regalloc
#138660 opened May 6, 2025 by optimisan Loading…
2
Revert "[InlineSpiller] Check rematerialization before folding operand (#134015)" backend:X86 llvm:regalloc
#137801 opened Apr 29, 2025 by arsenm Loading…
7
[X86][BreakFalseDeps] Using reverse order for undef register selection backend:X86 llvm:regalloc tablegen
#137569 opened Apr 28, 2025 by phoebewang Loading…
17
need help on the code in RegAllocGreedy.cpp->tryAssign() llvm:regalloc question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!
#135997 opened Apr 16, 2025 by BaoshanPang
[GreedyRegAlloc] Multiple spill reloads into same register without intermediate def/overwrite llvm:regalloc
#135639 opened Apr 14, 2025 by JanekvO
4
Address Codegen bug related to marking subregister MachineOperand defines as undef backend:AMDGPU llvm:regalloc
#134929 opened Apr 8, 2025 by bababuck Loading…
1
18
[RegisterCoalescer]: Try inflated RC for coalescing reg->subreg backend:AMDGPU llvm:regalloc
#134438 opened Apr 4, 2025 by jrbyrnes Loading…
9
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:AMDGPU backend:PowerPC backend:X86 llvm:regalloc
#134408 opened Apr 4, 2025 by sdesmalen-arm Loading…
6
[PHIElimination] Reuse existing COPY in predecessor basic block backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:SystemZ backend:X86 debuginfo llvm:globalisel llvm:regalloc llvm:transforms
#131837 opened Mar 18, 2025 by guy-david Loading…
6
[CodeGen] commuteInstruction should update implicit-def backend:X86 llvm:codegen llvm:regalloc
#131361 opened Mar 14, 2025 by sdesmalen-arm Loading…
9
[RegisterCoalescer]: Try inflated RC for coalescing backend:AMDGPU backend:PowerPC llvm:regalloc
#130870 opened Mar 12, 2025 by jrbyrnes Loading…
13
MachineVerifier does not diagnose REG_SEQUENCE with overlapping input operands accepts-invalid llvm:codegen llvm:regalloc
#130075 opened Mar 6, 2025 by arsenm
[WIP][CodeGen] Modifying MBB's liveins representation as into regUnits backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:m68k backend:X86 llvm:codegen llvm:globalisel llvm:regalloc tools:llvm-exegesis
#129847 opened Mar 5, 2025 by vg0204 Loading…
@vg0204
77
[AMDGPU][NPM] Support -regalloc-npm options backend:AMDGPU llvm:regalloc
#129035 opened Feb 27, 2025 by optimisan Loading…
13
Suboptimal register use on x86-64 backend:X86 llvm:regalloc
#128722 opened Feb 25, 2025 by tavianator
6
AMDGPU should try to shrink 64-bit defs to 32-bit when rematerializing backend:AMDGPU llvm:regalloc missed-optimization
#128716 opened Feb 25, 2025 by arsenm
3
LiveIntervals: Use BumpPtrAllocator llvm:regalloc
#127057 opened Feb 13, 2025 by arsenm Loading…
9
AMDGPU: No live subrange at use for an undef subreg right after LIS creation with partially defined register backend:AMDGPU llvm:regalloc
#125948 opened Feb 5, 2025 by rampitec
1
Lousy spilling in the RegAlloc's llvm:regalloc
#124350 opened Jan 24, 2025 by Bob64375
Use not jointly dominated by defs during scheduling with overlapping register tuple defs llvm:codegen llvm:regalloc
#123301 opened Jan 17, 2025 by arsenm
[TableGen][GISel] Create untyped registers during instruction selection backend:AMDGPU llvm:globalisel llvm:regalloc tablegen
#121270 opened Dec 28, 2024 by s-barannikov Loading…
24
[SystemZ] Bad machine code: Illegal virtual register for instruction backend:SystemZ llvm:regalloc
#121232 opened Dec 27, 2024 by JonPsson1
2
ProTip! Follow long discussions with comments:>50.