Skip to content

BPF: Ensure __sync_fetch_and_add() always generate atomic_fetch_add insn #101428

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Aug 5, 2024
Merged

BPF: Ensure __sync_fetch_and_add() always generate atomic_fetch_add insn #101428

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 0 additions & 2 deletions llvm/lib/Target/BPF/BPF.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,6 @@ FunctionPass *createBPFISelDag(BPFTargetMachine &TM);
FunctionPass *createBPFMISimplifyPatchablePass();
FunctionPass *createBPFMIPeepholePass();
FunctionPass *createBPFMIPreEmitPeepholePass();
FunctionPass *createBPFMIPreEmitCheckingPass();

InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &,
const BPFSubtarget &,
Expand All @@ -37,7 +36,6 @@ InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &,
void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
void initializeBPFDAGToDAGISelLegacyPass(PassRegistry &);
void initializeBPFMIPeepholePass(PassRegistry &);
void initializeBPFMIPreEmitCheckingPass(PassRegistry&);
void initializeBPFMIPreEmitPeepholePass(PassRegistry &);
void initializeBPFMISimplifyPatchablePass(PassRegistry &);

Expand Down
17 changes: 9 additions & 8 deletions llvm/lib/Target/BPF/BPFInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -789,12 +789,12 @@ let Predicates = [BPFNoALU32] in {
}

// Atomic XADD for BPFNoALU32
class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
class XADD<BPFWidthModifer SizeOp, string OpcodeStr>
: TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value,
(outs GPR:$dst),
(ins MEMri:$addr, GPR:$val),
"lock *("#OpcodeStr#" *)($addr) += $val",
[(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
[]> {
bits<4> dst;
bits<20> addr;

Expand All @@ -805,12 +805,6 @@ class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
let BPFClass = BPF_STX;
}

let Constraints = "$dst = $val" in {
let Predicates = [BPFNoALU32] in {
def XADDW : XADD<BPF_W, "u32", atomic_load_add_i32>;
}
}

// Atomic add, and, or, xor
class ATOMIC_NOFETCH<BPFArithOp Opc, string Opstr>
: TYPE_LD_ST<BPF_ATOMIC.Value, BPF_DW.Value,
Expand Down Expand Up @@ -895,6 +889,13 @@ class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr,
let BPFClass = BPF_STX;
}

let Constraints = "$dst = $val" in {
let Predicates = [BPFNoALU32] in {
def XADDW : XADD<BPF_W, "u32">;
def XFADDW : XFALU64<BPF_W, BPF_ADD, "u32", "add", atomic_load_add_i32>;
}
}

let Constraints = "$dst = $val" in {
let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
def XFADDW32 : XFALU32<BPF_W, BPF_ADD, "u32", "add", atomic_load_add_i32>;
Expand Down
251 changes: 0 additions & 251 deletions llvm/lib/Target/BPF/BPFMIChecking.cpp
View file
Open in desktop

This file was deleted.

1 change: 0 additions & 1 deletion llvm/lib/Target/BPF/BPFTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -178,7 +178,6 @@ void BPFPassConfig::addMachineSSAOptimization() {
}

void BPFPassConfig::addPreEmitPass() {
addPass(createBPFMIPreEmitCheckingPass());
if (getOptLevel() != CodeGenOptLevel::None)
if (!DisableMIPeephole)
addPass(createBPFMIPreEmitPeepholePass());
Expand Down
1 change: 0 additions & 1 deletion llvm/lib/Target/BPF/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,6 @@ add_llvm_target(BPFCodeGen
BPFSubtarget.cpp
BPFTargetMachine.cpp
BPFMIPeephole.cpp
BPFMIChecking.cpp
BPFMISimplifyPatchable.cpp
BTFDebug.cpp

Expand Down
17 changes: 7 additions & 10 deletions llvm/test/CodeGen/BPF/atomics.ll
View file
Open in desktop
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nitpick, the CHECKs could be simplified a bit, e.g.:

; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding -mcpu=v3 | FileCheck --check-prefix=CHECK-V3 %s

; CHECK-LABEL: test_load_add_32
; CHECK: r2 = atomic_fetch_add((u32 *)(r1 + 0), r2)
; CHECK-V3: w2 = atomic_fetch_add((u32 *)(r1 + 0), w2)
; CHECK: encoding: [0xc3,0x21,0x00,0x00,0x01,0x00,0x00,0x00]
define void @test_load_add_32(ptr %p, i32 zeroext %v) {
entry:
  atomicrmw add ptr %p, i32 %v seq_cst
  ret void
}

; CHECK-LABEL: test_load_add_64
; CHECK: r2 = atomic_fetch_add((u64 *)(r1 + 0), r2)
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x01,0x00,0x00,0x00]
define void @test_load_add_64(ptr %p, i64 zeroext %v) {
entry:
  atomicrmw add ptr %p, i64 %v seq_cst
  ret void
}

On the other hand, it looks like we should change the dis-assembler to avoid the discrepancy:

; CHECK: r2 = atomic_fetch_add((u32 *)(r1 + 0), r2)
; CHECK-V3: w2 = atomic_fetch_add((u32 *)(r1 + 0), w2)

Since instruction encoding is the same.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks. Indeed simplified CHECKs a little bit.
For the difference for

; CHECK: r2 = atomic_fetch_add((u32 *)(r1 + 0), r2)
; CHECK-V3: w2 = atomic_fetch_add((u32 *)(r1 + 0), w2)

I think it is okay, since this is asm output from llc.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do you mind if I try to change this behaviour for both llc and disasm? (in a separate pr)

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do you mind if I try to change this behaviour for both llc and disasm? (in a separate pr)

I don't know what code change you intend to do. But you can go ahead to send a patch and so we can discuss the change.

Original file line number Diff line number Diff line change
@@ -1,22 +1,19 @@
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding -mcpu=v3 | FileCheck --check-prefix=CHECK-V3 %s
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck --check-prefixes=CHECK,CHECK-V2 %s
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding -mcpu=v3 | FileCheck --check-prefixes=CHECK,CHECK-V3 %s

; CHECK-LABEL: test_load_add_32
; CHECK: lock *(u32 *)(r1 + 0) += r2
; CHECK: encoding: [0xc3,0x21
; CHECK-V3: lock *(u32 *)(r1 + 0) += w2
; CHECK-V3: encoding: [0xc3,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-V2: r2 = atomic_fetch_add((u32 *)(r1 + 0), r2)
; CHECK-V3: w2 = atomic_fetch_add((u32 *)(r1 + 0), w2)
; CHECK: encoding: [0xc3,0x21,0x00,0x00,0x01,0x00,0x00,0x00]
define void @test_load_add_32(ptr %p, i32 zeroext %v) {
entry:
atomicrmw add ptr %p, i32 %v seq_cst
ret void
}

; CHECK-LABEL: test_load_add_64
; CHECK: lock *(u64 *)(r1 + 0) += r2
; CHECK: encoding: [0xdb,0x21
; CHECK-V3: lock *(u64 *)(r1 + 0) += r2
; CHECK-V3: encoding: [0xdb,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: r2 = atomic_fetch_add((u64 *)(r1 + 0), r2)
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x01,0x00,0x00,0x00]
define void @test_load_add_64(ptr %p, i64 zeroext %v) {
entry:
atomicrmw add ptr %p, i64 %v seq_cst
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/BPF/atomics_2.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -214,8 +214,8 @@ entry:
}

; CHECK-LABEL: test_atomic_xor_32
; CHECK: lock *(u32 *)(r1 + 0) ^= w2
; CHECK: encoding: [0xc3,0x21,0x00,0x00,0xa0,0x00,0x00,0x00]
; CHECK: w2 = atomic_fetch_xor((u32 *)(r1 + 0), w2)
; CHECK: encoding: [0xc3,0x21,0x00,0x00,0xa1,0x00,0x00,0x00]
; CHECK: w0 = 0
define dso_local i32 @test_atomic_xor_32(ptr nocapture %p, i32 %v) local_unnamed_addr {
entry:
Expand All @@ -224,8 +224,8 @@ entry:
}

; CHECK-LABEL: test_atomic_xor_64
; CHECK: lock *(u64 *)(r1 + 0) ^= r2
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0xa0,0x00,0x00,0x00]
; CHECK: r2 = atomic_fetch_xor((u64 *)(r1 + 0), r2)
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0xa1,0x00,0x00,0x00]
; CHECK: w0 = 0
define dso_local i32 @test_atomic_xor_64(ptr nocapture %p, i64 %v) local_unnamed_addr {
entry:
Expand All @@ -234,8 +234,8 @@ entry:
}

; CHECK-LABEL: test_atomic_and_64
; CHECK: lock *(u64 *)(r1 + 0) &= r2
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x50,0x00,0x00,0x00]
; CHECK: r2 = atomic_fetch_and((u64 *)(r1 + 0), r2)
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x51,0x00,0x00,0x00]
; CHECK: w0 = 0
define dso_local i32 @test_atomic_and_64(ptr nocapture %p, i64 %v) local_unnamed_addr {
entry:
Expand All @@ -244,8 +244,8 @@ entry:
}

; CHECK-LABEL: test_atomic_or_64
; CHECK: lock *(u64 *)(r1 + 0) |= r2
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x40,0x00,0x00,0x00]
; CHECK: r2 = atomic_fetch_or((u64 *)(r1 + 0), r2)
; CHECK: encoding: [0xdb,0x21,0x00,0x00,0x41,0x00,0x00,0x00]
; CHECK: w0 = 0
define dso_local i32 @test_atomic_or_64(ptr nocapture %p, i64 %v) local_unnamed_addr {
entry:
Expand Down
Loading
Loading