[CodeGen][NFC] Add wrapper method for MBBMap #101893
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This is a preparation for changing the data structure of MBBMap.
llvmbot
added
backend:ARM
backend:AArch64
backend:PowerPC
backend:WebAssembly
backend:X86
llvm:SelectionDAG
|
@llvm/pr-subscribers-backend-arm @llvm/pr-subscribers-llvm-selectiondag Author: Alexis Engelke (aengelke) ChangesThis is a preparation for changing the data structure of MBBMap. Patch is 26.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/101893.diff 11 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
index 04667c04a4ef4..0e08b9bef11aa 100644
--- a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
+++ b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
@@ -212,6 +212,10 @@ class FunctionLoweringInfo {
return ValueMap.count(V);
}
+ MachineBasicBlock *getMBB(const BasicBlock *BB) const {
+ return MBBMap.lookup(BB);
+ }
+
Register CreateReg(MVT VT, bool isDivergent = false);
Register CreateRegs(const Value *V);
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index e255bbaa92b16..517e3533e7729 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1833,7 +1833,7 @@ bool FastISel::selectOperator(const User *I, unsigned Opcode) {
if (BI->isUnconditional()) {
const BasicBlock *LLVMSucc = BI->getSuccessor(0);
- MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
+ MachineBasicBlock *MSucc = FuncInfo.getMBB(LLVMSucc);
fastEmitBranch(MSucc, BI->getDebugLoc());
return true;
}
@@ -2243,7 +2243,7 @@ bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
for (const BasicBlock *SuccBB : successors(LLVMBB)) {
if (!isa<PHINode>(SuccBB->begin()))
continue;
- MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
+ MachineBasicBlock *SuccMBB = FuncInfo.getMBB(SuccBB);
// If this terminator has multiple identical successors (common for
// switches), only handle each succ once.
@@ -2367,7 +2367,7 @@ bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
return false;
// Must be in the same basic block.
if (isa<Instruction>(Add) &&
- FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
+ FuncInfo.getMBB(cast<Instruction>(Add)->getParent()) != FuncInfo.MBB)
return false;
// Must have a constant operand.
return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 8f5b05b662b33..9ca76aa09a2fa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -307,20 +307,16 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
for (WinEHHandlerType &H : TBME.HandlerArray) {
if (H.Handler)
- H.Handler = MBBMap[cast<const BasicBlock *>(H.Handler)];
+ H.Handler = getMBB(cast<const BasicBlock *>(H.Handler));
}
}
for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
if (UME.Cleanup)
- UME.Cleanup = MBBMap[cast<const BasicBlock *>(UME.Cleanup)];
- for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
- const auto *BB = cast<const BasicBlock *>(UME.Handler);
- UME.Handler = MBBMap[BB];
- }
- for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
- const auto *BB = cast<const BasicBlock *>(CME.Handler);
- CME.Handler = MBBMap[BB];
- }
+ UME.Cleanup = getMBB(cast<const BasicBlock *>(UME.Cleanup));
+ for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap)
+ UME.Handler = getMBB(cast<const BasicBlock *>(UME.Handler));
+ for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap)
+ CME.Handler = getMBB(cast<const BasicBlock *>(CME.Handler));
} else if (Personality == EHPersonality::Wasm_CXX) {
WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
calculateWasmEHInfo(&fn, EHInfo);
@@ -330,16 +326,16 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
for (auto &KV : EHInfo.SrcToUnwindDest) {
const auto *Src = cast<const BasicBlock *>(KV.first);
const auto *Dest = cast<const BasicBlock *>(KV.second);
- SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest];
+ SrcToUnwindDest[getMBB(Src)] = getMBB(Dest);
}
EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs;
for (auto &KV : EHInfo.UnwindDestToSrcs) {
const auto *Dest = cast<const BasicBlock *>(KV.first);
- UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>();
+ MachineBasicBlock *DestMBB = getMBB(Dest);
+ UnwindDestToSrcs[DestMBB] = SmallPtrSet<BBOrMBB, 4>();
for (const auto P : KV.second)
- UnwindDestToSrcs[MBBMap[Dest]].insert(
- MBBMap[cast<const BasicBlock *>(P)]);
+ UnwindDestToSrcs[DestMBB].insert(getMBB(cast<const BasicBlock *>(P)));
}
EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a035fee6aafca..9d617c7acd13c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1952,7 +1952,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
return DAG.getMDNode(cast<MDNode>(MD->getMetadata()));
if (const auto *BB = dyn_cast<BasicBlock>(V))
- return DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
+ return DAG.getBasicBlock(FuncInfo.getMBB(BB));
llvm_unreachable("Can't get register for value!");
}
@@ -1972,7 +1972,7 @@ void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
// Update machine-CFG edge.
- MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
+ MachineBasicBlock *TargetMBB = FuncInfo.getMBB(I.getSuccessor());
FuncInfo.MBB->addSuccessor(TargetMBB);
TargetMBB->setIsEHCatchretTarget(true);
DAG.getMachineFunction().setHasEHCatchret(true);
@@ -2000,7 +2000,7 @@ void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
else
SuccessorColor = cast<Instruction>(ParentPad)->getParent();
assert(SuccessorColor && "No parent funclet for catchret!");
- MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
+ MachineBasicBlock *SuccessorColorMBB = FuncInfo.getMBB(SuccessorColor);
assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
// Create the terminator node.
@@ -2056,14 +2056,14 @@ static void findWasmUnwindDestinations(
const Instruction *Pad = EHPadBB->getFirstNonPHI();
if (isa<CleanupPadInst>(Pad)) {
// Stop on cleanup pads.
- UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
+ UnwindDests.emplace_back(FuncInfo.getMBB(EHPadBB), Prob);
UnwindDests.back().first->setIsEHScopeEntry();
break;
} else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
// Add the catchpad handlers to the possible destinations. We don't
// continue to the unwind destination of the catchswitch for wasm.
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
- UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
+ UnwindDests.emplace_back(FuncInfo.getMBB(CatchPadBB), Prob);
UnwindDests.back().first->setIsEHScopeEntry();
}
break;
@@ -2105,19 +2105,19 @@ static void findUnwindDestinations(
BasicBlock *NewEHPadBB = nullptr;
if (isa<LandingPadInst>(Pad)) {
// Stop on landingpads. They are not funclets.
- UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
+ UnwindDests.emplace_back(FuncInfo.getMBB(EHPadBB), Prob);
break;
} else if (isa<CleanupPadInst>(Pad)) {
// Stop on cleanup pads. Cleanups are always funclet entries for all known
// personalities.
- UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
+ UnwindDests.emplace_back(FuncInfo.getMBB(EHPadBB), Prob);
UnwindDests.back().first->setIsEHScopeEntry();
UnwindDests.back().first->setIsEHFuncletEntry();
break;
} else if (const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
// Add the catchpad handlers to the possible destinations.
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
- UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
+ UnwindDests.emplace_back(FuncInfo.getMBB(CatchPadBB), Prob);
// For MSVC++ and the CLR, catchblocks are funclets and need prologues.
if (IsMSVCCXX || IsCoreCLR)
UnwindDests.back().first->setIsEHFuncletEntry();
@@ -2777,7 +2777,7 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
MachineBasicBlock *BrMBB = FuncInfo.MBB;
// Update machine-CFG edges.
- MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
+ MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(I.getSuccessor(0));
if (I.isUnconditional()) {
// Update machine-CFG edges.
@@ -2799,7 +2799,7 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
// If this condition is one of the special cases we handle, do special stuff
// now.
const Value *CondVal = I.getCondition();
- MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
+ MachineBasicBlock *Succ1MBB = FuncInfo.getMBB(I.getSuccessor(1));
// If this is a series of conditions that are or'd or and'd together, emit
// this as a sequence of branches instead of setcc's with and/or operations.
@@ -3317,9 +3317,9 @@ void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
// Retrieve successors. Look through artificial IR level blocks like
// catchswitch for successors.
- MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
+ MachineBasicBlock *Return = FuncInfo.getMBB(I.getSuccessor(0));
const BasicBlock *EHPadBB = I.getSuccessor(1);
- MachineBasicBlock *EHPadMBB = FuncInfo.MBBMap[EHPadBB];
+ MachineBasicBlock *EHPadMBB = FuncInfo.getMBB(EHPadBB);
// Deopt and ptrauth bundles are lowered in helper functions, and we don't
// have to do anything here to lower funclet bundles.
@@ -3427,13 +3427,13 @@ void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
// Retrieve successors.
SmallPtrSet<BasicBlock *, 8> Dests;
Dests.insert(I.getDefaultDest());
- MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
+ MachineBasicBlock *Return = FuncInfo.getMBB(I.getDefaultDest());
// Update successor info.
addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne());
for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
BasicBlock *Dest = I.getIndirectDest(i);
- MachineBasicBlock *Target = FuncInfo.MBBMap[Dest];
+ MachineBasicBlock *Target = FuncInfo.getMBB(Dest);
Target->setIsInlineAsmBrIndirectTarget();
Target->setMachineBlockAddressTaken();
Target->setLabelMustBeEmitted();
@@ -3525,7 +3525,7 @@ void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
if (!Inserted)
continue;
- MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
+ MachineBasicBlock *Succ = FuncInfo.getMBB(BB);
addSuccessorWithProb(IndirectBrMBB, Succ);
}
IndirectBrMBB->normalizeSuccProbs();
@@ -8628,7 +8628,7 @@ SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain,
unsigned CallSiteIndex = FuncInfo.getCurrentCallSite();
if (CallSiteIndex) {
MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
- LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
+ LPadToCallSiteMap[FuncInfo.getMBB(EHPadBB)].push_back(CallSiteIndex);
// Now that the call site is handled, stop tracking it.
FuncInfo.setCurrentCallSite(0);
@@ -8659,7 +8659,7 @@ SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II,
EHInfo->addIPToStateRange(II, BeginLabel, EndLabel);
} else if (!isScopedEHPersonality(Pers)) {
assert(EHPadBB);
- MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
+ MF.addInvoke(FuncInfo.getMBB(EHPadBB), BeginLabel, EndLabel);
}
return Chain;
@@ -11826,7 +11826,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
// block.
for (const BasicBlock *SuccBB : successors(LLVMBB->getTerminator())) {
if (!isa<PHINode>(SuccBB->begin())) continue;
- MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
+ MachineBasicBlock *SuccMBB = FuncInfo.getMBB(SuccBB);
// If this terminator has multiple identical successors (common for
// switches), only handle each succ once.
@@ -12306,7 +12306,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
CaseClusterVector Clusters;
Clusters.reserve(SI.getNumCases());
for (auto I : SI.cases()) {
- MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
+ MachineBasicBlock *Succ = FuncInfo.getMBB(I.getCaseSuccessor());
const ConstantInt *CaseVal = I.getCaseValue();
BranchProbability Prob =
BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
@@ -12314,7 +12314,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
}
- MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
+ MachineBasicBlock *DefaultMBB = FuncInfo.getMBB(SI.getDefaultDest());
// Cluster adjacent cases with the same destination. We do this at all
// optimization levels because it's cheap to do and will make codegen faster
@@ -12368,7 +12368,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
// Scale the branchprobability for DefaultMBB if the peel occurs and
// DefaultMBB is not replaced.
if (PeeledCaseProb != BranchProbability::getZero() &&
- DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()])
+ DefaultMBB == FuncInfo.getMBB(SI.getDefaultDest()))
DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb);
WorkList.push_back(
{PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 607c8031480c0..95b6d27d31eea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1591,7 +1591,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
++NumEntryBlocks;
// Set up FuncInfo for ISel. Entry blocks never have PHIs.
- FuncInfo->MBB = FuncInfo->MBBMap[&Fn.getEntryBlock()];
+ FuncInfo->MBB = FuncInfo->getMBB(&Fn.getEntryBlock());
FuncInfo->InsertPt = FuncInfo->MBB->begin();
CurDAG->setFunctionLoweringInfo(FuncInfo.get());
@@ -1669,7 +1669,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
BasicBlock::const_iterator const End = LLVMBB->end();
BasicBlock::const_iterator BI = End;
- FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
+ FuncInfo->MBB = FuncInfo->getMBB(LLVMBB);
if (!FuncInfo->MBB)
continue; // Some blocks like catchpads have no code or MBB.
@@ -1821,7 +1821,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (SP->shouldEmitSDCheck(*LLVMBB)) {
bool FunctionBasedInstrumentation =
TLI->getSSPStackGuardCheck(*Fn.getParent());
- SDB->SPDescriptor.initialize(LLVMBB, FuncInfo->MBBMap[LLVMBB],
+ SDB->SPDescriptor.initialize(LLVMBB, FuncInfo->getMBB(LLVMBB),
FunctionBasedInstrumentation);
}
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 719d79dec0c31..cbf38f2c57a35 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -597,7 +597,7 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
// Don't walk into other basic blocks unless the object is an alloca from
// another block, otherwise it may not have a virtual register assigned.
if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
- FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
+ FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB) {
Opcode = I->getOpcode();
U = I;
}
@@ -749,7 +749,7 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
const Value *Src = U->getOperand(0);
if (const auto *I = dyn_cast<Instruction>(Src)) {
- if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
+ if (FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB) {
// Fold the zext or sext when it won't become a noop.
if (const auto *ZE = dyn_cast<ZExtInst>(I)) {
if (!isIntExtFree(ZE) &&
@@ -831,7 +831,7 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
const Value *Src = LHS;
if (const auto *I = dyn_cast<Instruction>(Src)) {
- if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
+ if (FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB) {
// Fold the zext or sext when it won't become a noop.
if (const auto *ZE = dyn_cast<ZExtInst>(I)) {
if (!isIntExtFree(ZE) &&
@@ -1027,7 +1027,7 @@ bool AArch64FastISel::isValueAvailable(const Value *V) const {
return true;
const auto *I = cast<Instruction>(V);
- return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
+ return FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB;
}
bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
@@ -2279,8 +2279,8 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
if (BW > 64)
return false;
- MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
- MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
+ MachineBasicBlock *TBB = FuncInfo.getMBB(BI->getSuccessor(0));
+ MachineBasicBlock *FBB = FuncInfo.getMBB(BI->getSuccessor(1));
// Try to take advantage of fallthrough opportunities.
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
@@ -2384,13 +2384,13 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
bool AArch64FastISel::selectBranch(const Instruction *I) {
const BranchInst *BI = cast<BranchInst>(I);
if (BI->isUnconditional()) {
- MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
+ MachineBasicBlock *MSucc = FuncInfo.getMBB(BI->getSuccessor(0));
fastEmitBranch(MSucc, BI->getDebugLoc());
return true;
}
- MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
- MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
+ MachineBasicBlock *TBB = FuncInfo.getMBB(BI->getSuccessor(0));
+ MachineBasicBlock *FBB = FuncInfo.getMBB(BI->getSuccessor(1));
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
if (CI->hasOneUse() && isValueAvailable(CI)) {
@@ -2527,7 +2527,7 @@ bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
// Make sure the CFG is up-to-date.
for (const auto *Succ : BI->successors())
- FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[Succ]);
+ FuncInfo.MBB->addSuccessor(FuncInfo.getMBB(Succ));
return true;
}
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 1cc21da51d1e6..1761c25c63dba 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -700,7 +700,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
// Don't walk into other basic blocks unless the object is an alloca from
// another block, otherwise it may not have a virtual register assigned.
if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
- FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
+ FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB) {
Opcode = I->getOpcode();
U = I;
}
@@ -1223,8 +1223,8 @@ static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
bool ARMFastISel::SelectBranch(const Instruction *I) {
const BranchInst *BI = cast<BranchInst>(I);
- MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
- MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
+ MachineBasicBlock *TBB = FuncInfo.getMBB(BI->getSuccessor(0));
+ MachineBasicBlock *FBB = FuncInfo.getMBB(BI->getSuccessor(1));
// Simple branch support.
@@ -1329,7 +1329,7 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
const IndirectBrInst *IB = cast<IndirectBrInst>(I);
for (const BasicBl...
[truncated]
|
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This is a preparation for changing the data structure of MBBMap.