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Reapply "[AMDGPU] Always lower s/udiv64 by constant to MUL" #101942

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Merged
merged 2 commits into from
Aug 12, 2024
Merged

Reapply "[AMDGPU] Always lower s/udiv64 by constant to MUL" #101942

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4903632
Reapply "[AMDGPU] Always lower s/udiv64 by constant to MUL"
Pierre-vh Aug 2, 2024
c9665ce
update test
Pierre-vh Aug 12, 2024
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2 changes: 2 additions & 0 deletions llvm/include/llvm/CodeGen/TargetLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5082,8 +5082,10 @@ class TargetLowering : public TargetLoweringBase {
//

SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
bool IsAfterLegalTypes,
SmallVectorImpl<SDNode *> &Created) const;
SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
bool IsAfterLegalTypes,
SmallVectorImpl<SDNode *> &Created) const;
// Build sdiv by power-of-2 with conditional move instructions
SDValue buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -27800,7 +27800,7 @@ SDValue DAGCombiner::BuildSDIV(SDNode *N) {
return SDValue();

SmallVector<SDNode *, 8> Built;
if (SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, Built)) {
if (SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, LegalTypes, Built)) {
for (SDNode *N : Built)
AddToWorklist(N);
return S;
Expand Down Expand Up @@ -27841,7 +27841,7 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N) {
return SDValue();

SmallVector<SDNode *, 8> Built;
if (SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, Built)) {
if (SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, LegalTypes, Built)) {
for (SDNode *N : Built)
AddToWorklist(N);
return S;
Expand Down
16 changes: 14 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6285,6 +6285,7 @@ SDValue TargetLowering::buildSDIVPow2WithCMov(
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
bool IsAfterLegalization,
bool IsAfterLegalTypes,
SmallVectorImpl<SDNode *> &Created) const {
SDLoc dl(N);
EVT VT = N->getValueType(0);
Expand Down Expand Up @@ -6405,7 +6406,12 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
if (VT.isVector())
WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
VT.getVectorElementCount());
if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
// Some targets like AMDGPU try to go from SDIV to SDIVREM which is then
// custom lowered. This is very expensive so avoid it at all costs for
// constant divisors.
if ((!IsAfterLegalTypes && isOperationExpand(ISD::SDIV, VT) &&
isOperationCustom(ISD::SDIVREM, VT.getScalarType())) ||
isOperationLegalOrCustom(ISD::MUL, WideVT)) {
X = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, X);
Y = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, Y);
Y = DAG.getNode(ISD::MUL, dl, WideVT, X, Y);
Expand Down Expand Up @@ -6447,6 +6453,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
bool IsAfterLegalization,
bool IsAfterLegalTypes,
SmallVectorImpl<SDNode *> &Created) const {
SDLoc dl(N);
EVT VT = N->getValueType(0);
Expand Down Expand Up @@ -6588,7 +6595,12 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
if (VT.isVector())
WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
VT.getVectorElementCount());
if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
// Some targets like AMDGPU try to go from UDIV to UDIVREM which is then
// custom lowered. This is very expensive so avoid it at all costs for
// constant divisors.
if ((!IsAfterLegalTypes && isOperationExpand(ISD::UDIV, VT) &&
isOperationCustom(ISD::UDIVREM, VT.getScalarType())) ||
isOperationLegalOrCustom(ISD::MUL, WideVT)) {
X = DAG.getNode(ISD::ZERO_EXTEND, dl, WideVT, X);
Y = DAG.getNode(ISD::ZERO_EXTEND, dl, WideVT, Y);
Y = DAG.getNode(ISD::MUL, dl, WideVT, X, Y);
Expand Down
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