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[AArch64][GlobalISel] Disable fixed-point iteration in all Combiners #102167

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Merged
merged 4 commits into from
Aug 16, 2024
Merged

[AArch64][GlobalISel] Disable fixed-point iteration in all Combiners #102167

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694cf50
[𝘀𝗽𝗿] changes to main this commit is based on
tobias-stadler Aug 6, 2024
c847a45
[𝘀𝗽𝗿] initial version
tobias-stadler Aug 6, 2024
cc2dbb7
[spr] changes introduced through rebase
tobias-stadler Aug 16, 2024
f15da38
Rebase
tobias-stadler Aug 16, 2024
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -566,6 +566,11 @@ bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// Legalizer performs DCE, so a full DCE pass is unnecessary.
CInfo.EnableFullDCE = false;
AArch64PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, CSEInfo,
RuleConfig, ST, MDT, LI);
bool Changed = Impl.combineMachineInstrs();
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
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Expand Up @@ -1296,6 +1296,11 @@ bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) {
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, /*OptEnabled=*/true,
F.hasOptSize(), F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// PostLegalizerCombiner performs DCE, so a full DCE pass is unnecessary.
CInfo.EnableFullDCE = false;
AArch64PostLegalizerLoweringImpl Impl(MF, CInfo, TPC, /*CSEInfo*/ nullptr,
RuleConfig, ST);
return Impl.combineMachineInstrs();
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
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Expand Up @@ -861,6 +861,12 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// This is the first Combiner, so the input IR might contain dead
// instructions.
CInfo.EnableFullDCE = true;
AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB, CSEInfo,
RuleConfig, ST, MDT, LI);
return Impl.combineMachineInstrs();
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
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Expand Up @@ -203,8 +203,8 @@ body: |
; CHECK-LABEL: name: test_icmp_and_icmp_9_2
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[C]](s64)
; CHECK-NEXT: %zext:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY %zext(s64)
%0:_(s64) = COPY $x0
%nine:_(s64) = G_CONSTANT i64 9
%two:_(s64) = G_CONSTANT i64 2
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
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Expand Up @@ -76,9 +76,9 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %o_wide:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: $w1 = COPY [[C]](s32)
; CHECK-NEXT: $w1 = COPY %o_wide(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
Expand All @@ -101,10 +101,10 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: %const:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %o_wide:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: $w1 = COPY [[COPY]](s32)
; CHECK-NEXT: $w2 = COPY %const(s32)
; CHECK-NEXT: $w2 = COPY %o_wide(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%const:_(s32) = G_CONSTANT i32 0
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
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Expand Up @@ -257,10 +257,10 @@ define i32 @udiv_div_by_180(i32 %x)
;
; GISEL-LABEL: udiv_div_by_180:
; GISEL: // %bb.0:
; GISEL-NEXT: uxtb w8, w0
; GISEL-NEXT: mov w9, #5826 // =0x16c2
; GISEL-NEXT: movk w9, #364, lsl #16
; GISEL-NEXT: umull x8, w8, w9
; GISEL-NEXT: mov w8, #5826 // =0x16c2
; GISEL-NEXT: and w9, w0, #0xff
; GISEL-NEXT: movk w8, #364, lsl #16
; GISEL-NEXT: umull x8, w9, w8
Comment on lines +260 to +263
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@tobias-stadler tobias-stadler Aug 6, 2024 •
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expanding the div generates a bunch of instructions and the order in which the combines are applied results in different ouput

; GISEL-NEXT: lsr x0, x8, #32
; GISEL-NEXT: // kill: def $w0 killed $w0 killed $x0
; GISEL-NEXT: ret
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
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Expand Up @@ -151,9 +151,9 @@ body: |
; CHECK-LABEL: name: ptr_add_chain
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @g + 1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: %dont_fold_me:_(p0) = G_PTR_ADD [[GV]], [[C]](s64)
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @g + 4
; CHECK-NEXT: %offset:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: %dont_fold_me:_(p0) = G_PTR_ADD [[GV]], %offset(s64)
; CHECK-NEXT: $x0 = COPY %dont_fold_me(p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%global:_(p0) = G_GLOBAL_VALUE @g
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
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Expand Up @@ -9,6 +9,8 @@ body: |
bb.1:
; CHECK-LABEL: name: crash_fn
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
Comment on lines +12 to +13
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These are dead in the input IR, which doesn't happen inside the CodeGen pipeline.

; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16), align 8)
; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16))
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD1]], [[ZEXTLOAD]]
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16 changes: 12 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
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Expand Up @@ -64,21 +64,28 @@ body: |
; LOWER-NEXT: {{ $}}
; LOWER-NEXT: %reg0:_(s64) = COPY $x0
; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
; LOWER-NEXT: %reg1:_(s64) = COPY $x1
; LOWER-NEXT: %cmp1:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %reg1
; LOWER-NEXT: %add:_(s64) = G_ADD %cmp_lhs, %reg0
; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
; LOWER-NEXT: $w0 = COPY %cmp2(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; LOWER-NEXT: $w1 = COPY %cmp1(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0, implicit $w1
;
; SELECT-LABEL: name: dont_swap_more_than_one_use
; SELECT: liveins: $x0, $x1
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT-NEXT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7
; SELECT-NEXT: %reg1:gpr64 = COPY $x1
; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %reg1, implicit-def $nzcv
; SELECT-NEXT: %cmp1:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0
; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
; SELECT-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
; SELECT-NEXT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp2
; SELECT-NEXT: RET_ReallyLR implicit $w0
; SELECT-NEXT: $w1 = COPY %cmp1
; SELECT-NEXT: RET_ReallyLR implicit $w0, implicit $w1
%reg0:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
%reg1:_(s64) = COPY $x1
Expand All @@ -88,7 +95,8 @@ body: |
%cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add

$w0 = COPY %cmp2(s32)
RET_ReallyLR implicit $w0
$w1 = COPY %cmp1(s32)
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@tobias-stadler tobias-stadler Aug 6, 2024 •
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cmp1 was dead in the input IR, but according to the comment this seems unintended, so I have fixed this.

RET_ReallyLR implicit $w0, implicit $w1

...
---
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/setcc_knownbits.ll
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Expand Up @@ -33,8 +33,7 @@ define noundef i1 @logger(i32 noundef %logLevel, ptr %ea, ptr %pll) {
; CHECK-GI-NEXT: b.hi .LBB1_2
; CHECK-GI-NEXT: // %bb.1: // %land.rhs
; CHECK-GI-NEXT: ldr x8, [x1]
; CHECK-GI-NEXT: ldrb w8, [x8]
; CHECK-GI-NEXT: and w0, w8, #0x1
; CHECK-GI-NEXT: ldrb w0, [x8]
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The immediate DCEing and better ordering of combines prevents the PreLegalizerCombiner from generating a bunch of useless artifacts that it can't combine away again. These artifacts are converted into G_AND by the ArtifactCombiner, which can't be combined away by the redundant_and combine, because KnownBits can't look through the implicit anyext of the G_LOAD. We are probably missing some combines that convert the load into sext/zext versions.

; CHECK-GI-NEXT: .LBB1_2: // %land.end
; CHECK-GI-NEXT: ret
entry:
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