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LSV: forbid load-cycles when vectorizing; fix bug #104815

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Merged
merged 4 commits into from
Aug 22, 2024
Merged

LSV: forbid load-cycles when vectorizing; fix bug #104815

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6bfb08b
LSV: forbid load-cycles when vectorizing; fix bug
artagnon Aug 19, 2024
4465fef
LSV: address review
artagnon Aug 19, 2024
cb2ab85
LSV: redo patch
artagnon Aug 20, 2024
e831e1a
LSV: strip bad comment
artagnon Aug 20, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1499,6 +1499,13 @@ std::optional<APInt> Vectorizer::getConstantOffset(Value *PtrA, Value *PtrB,

// Try to compute B - A.
const SCEV *DistScev = SE.getMinusSCEV(SE.getSCEV(PtrB), SE.getSCEV(PtrA));
if (DistScev->isZero()) {
// A load in the chain is dependent on another load in the chain, and
// attempting to vectorize this chain would create a cycle.
LLVM_DEBUG(dbgs() << "LSV: SCEV diff is zero; not vectorizing\n");
return std::nullopt;
}

if (DistScev != SE.getCouldNotCompute()) {
LLVM_DEBUG(dbgs() << "LSV: SCEV PtrB - PtrA =" << *DistScev << "\n");
ConstantRange DistRange = SE.getSignedRange(DistScev);
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21 changes: 17 additions & 4 deletions llvm/test/Transforms/LoadStoreVectorizer/AArch64/pr37865.ll
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@@ -1,9 +1,22 @@
; REQUIRES: asserts
; RUN: not --crash opt -mtriple=aarch64 -passes=load-store-vectorizer \
; RUN: -disable-output %s 2>&1 | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -mtriple=aarch64 -passes=load-store-vectorizer -S %s | FileCheck %s

; LSV was attempting to vectorize this earlier, but crashed while re-ordering
; instructions due to the load-load cycle. Now, the chain is no longer a
; candidate for vectorization.

define i32 @load_cycle(ptr %x) {
; CHECK: Unexpected cycle while re-ordering instructions
; CHECK-LABEL: define i32 @load_cycle(
; CHECK-SAME: ptr [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[GEP_X_1:%.*]] = getelementptr inbounds [2 x i32], ptr [[X]], i32 0, i32 1
; CHECK-NEXT: [[LOAD_X_1:%.*]] = load i32, ptr [[GEP_X_1]], align 4
; CHECK-NEXT: [[REM:%.*]] = urem i32 [[LOAD_X_1]], 1
; CHECK-NEXT: [[GEP_X_2:%.*]] = getelementptr inbounds [2 x i32], ptr [[X]], i32 [[REM]], i32 0
; CHECK-NEXT: [[LOAD_X_2:%.*]] = load i32, ptr [[GEP_X_2]], align 4
; CHECK-NEXT: [[RET:%.*]] = add i32 [[LOAD_X_2]], [[LOAD_X_1]]
; CHECK-NEXT: ret i32 [[RET]]
;
entry:
%gep.x.1 = getelementptr inbounds [2 x i32], ptr %x, i32 0, i32 1
%load.x.1 = load i32, ptr %gep.x.1
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