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[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners #105517

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Merged
merged 1 commit into from
Aug 22, 2024
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[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners #105517

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6 changes: 5 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -499,7 +499,11 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {

CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
LI, EnableOpt, F.hasOptSize(), F.hasMinSize());

// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// Legalizer performs DCE, so a full DCE pass is unnecessary.
CInfo.EnableFullDCE = false;
AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, /*CSEInfo*/ nullptr,
RuleConfig, ST, MDT, LI);
return Impl.combineMachineInstrs();
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
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Expand Up @@ -276,6 +276,12 @@ bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
: &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
nullptr, EnableOpt, F.hasOptSize(), F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// This is the first Combiner, so the input IR might contain dead
// instructions.
CInfo.EnableFullDCE = true;
AMDGPUPreLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, CSEInfo, RuleConfig,
STI, MDT, STI.getLegalizerInfo());
return Impl.combineMachineInstrs();
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
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Expand Up @@ -454,6 +454,12 @@ bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {

CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
LI, EnableOpt, F.hasOptSize(), F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
// RegBankSelect seems not to leave dead instructions, so a full DCE pass is
// unnecessary.
CInfo.EnableFullDCE = false;
AMDGPURegBankCombinerImpl Impl(MF, CInfo, TPC, *KB, /*CSEInfo*/ nullptr,
RuleConfig, ST, MDT, LI);
return Impl.combineMachineInstrs();
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8 changes: 8 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
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Expand Up @@ -203,6 +203,7 @@ body: |
; CHECK-LABEL: name: remove_and_65535_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
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I assume this copy was always here, and this test needs regeneration for some reason?

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Oh, this is just DCE disabled, but for the test purposes the copy shouldn't have been here in the first place

; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
Expand All @@ -225,6 +226,7 @@ body: |
; CHECK-LABEL: name: remove_and_131071_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: $vgpr0 = COPY %lds_size(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
Expand All @@ -245,6 +247,7 @@ body: |
; CHECK-LABEL: name: no_remove_and_65536_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 65536
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
Expand All @@ -267,6 +270,7 @@ body: |
; CHECK-LABEL: name: no_remove_and_32767_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 32767
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
Expand All @@ -291,6 +295,8 @@ body: |
; CHECK-LABEL: name: remove_and_umin_lhs_only
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %val:_(s32) = COPY $vgpr4
; CHECK-NEXT: %k255:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %umin0:_(s32) = G_UMIN %val, %k255
Expand All @@ -316,6 +322,8 @@ body: |
; CHECK-LABEL: name: remove_and_umin_rhs_only
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %val:_(s32) = COPY $vgpr4
; CHECK-NEXT: %k255:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %umin0:_(s32) = G_UMIN %val, %k255
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