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[LoongArch] Codegen for concat_vectors with LASX #107523

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Merged
merged 1 commit into from
Sep 10, 2024
Merged

[LoongArch] Codegen for concat_vectors with LASX #107523

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1 change: 1 addition & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -296,6 +296,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);

setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
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6 changes: 6 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
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Expand Up @@ -1789,6 +1789,12 @@ def : Pat<(v4i32 (fp_to_uint (v4f64 LASX256:$vj))),
v4f64:$vj)),
sub_128)>;

// XVPERMI_Q
foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
def : Pat<(vt (concat_vectors LSX128:$vd, LSX128:$vj)),
(XVPERMI_Q (SUBREG_TO_REG (i64 0), LSX128:$vd, sub_128),
(SUBREG_TO_REG (i64 0), LSX128:$vj, sub_128), 2)>;

} // Predicates = [HasExtLASX]

/// Intrinsic pattern
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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
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@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

;; Without this patch(codegen for concat_vectors), the test will hang.
@g_156 = external global [12 x i32]
@g_490 = external global i32
@g_813 = external global i32

define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(g_156)
; CHECK-NEXT: ld.d $a0, $a0, %got_pc_lo12(g_156)
; CHECK-NEXT: pcalau12i $a1, %got_pc_hi20(g_490)
; CHECK-NEXT: ld.d $a1, $a1, %got_pc_lo12(g_490)
; CHECK-NEXT: ld.w $a2, $a0, 24
; CHECK-NEXT: pcalau12i $a3, %got_pc_hi20(g_813)
; CHECK-NEXT: ld.d $a3, $a3, %got_pc_lo12(g_813)
; CHECK-NEXT: st.w $zero, $a1, 0
; CHECK-NEXT: st.w $a2, $a3, 0
; CHECK-NEXT: vrepli.b $vr0, 0
; CHECK-NEXT: vst $vr0, $a0, 32
; CHECK-NEXT: xvpermi.q $xr0, $xr0, 2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: st.w $zero, $a0, 20
; CHECK-NEXT: ret
entry:
store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
store i32 0, ptr @g_490, align 4
%0 = load i32, ptr getelementptr inbounds (i8, ptr @g_156, i64 24), align 4
store i32 %0, ptr @g_813, align 4
tail call void @llvm.memset.p0.i64(ptr @g_156, i8 0, i64 48, i1 false)
store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
ret void
}
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