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[VectorCombine] Don't shrink lshr if the shamt is not less than bitwidth #108705

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Merged
merged 2 commits into from
Sep 15, 2024
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[VectorCombine] Don't shrink lshr if the shamt is not less than bitwidth #108705

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96f3521
[VectorCombine] Add pre-commit tests. NFC.
dtcxzyw Sep 15, 2024
fe91054
[VectorCombine] Don't shrink lshr if the shamt is not less than bitwidth
dtcxzyw Sep 15, 2024
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20 changes: 14 additions & 6 deletions llvm/lib/Transforms/Vectorize/VectorCombine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2597,11 +2597,19 @@ bool VectorCombine::shrinkType(llvm::Instruction &I) {
auto *SmallTy = cast<FixedVectorType>(ZExted->getType());
unsigned BW = SmallTy->getElementType()->getPrimitiveSizeInBits();

// Check that the expression overall uses at most the same number of bits as
// ZExted
KnownBits KB = computeKnownBits(&I, *DL);
if (KB.countMaxActiveBits() > BW)
return false;
if (I.getOpcode() == Instruction::LShr) {
// Check that the shift amount is less than the number of bits in the
// smaller type. Otherwise, the smaller lshr will return a poison value.
KnownBits ShAmtKB = computeKnownBits(I.getOperand(1), *DL);
if (ShAmtKB.getMaxValue().uge(BW))
return false;
} else {
// Check that the expression overall uses at most the same number of bits as
// ZExted
KnownBits KB = computeKnownBits(&I, *DL);
if (KB.countMaxActiveBits() > BW)
return false;
}

// Calculate costs of leaving current IR as it is and moving ZExt operation
// later, along with adding truncates if needed
Expand All @@ -2628,7 +2636,7 @@ bool VectorCombine::shrinkType(llvm::Instruction &I) {
return false;

// Check if we can propagate ZExt through its other users
KB = computeKnownBits(UI, *DL);
KnownBits KB = computeKnownBits(UI, *DL);
if (KB.countMaxActiveBits() > BW)
return false;

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13 changes: 13 additions & 0 deletions llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll
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Expand Up @@ -100,4 +100,17 @@ vector.body:
ret i32 %2
}

define <2 x i32> @pr108698(<2 x i64> %x, <2 x i32> %y) {
; CHECK-LABEL: @pr108698(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[EXT]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i32> [[LSHR]]
;
%cmp = icmp eq <2 x i64> %x, zeroinitializer
%ext = zext <2 x i1> %cmp to <2 x i32>
%lshr = lshr <2 x i32> %ext, %y
ret <2 x i32> %lshr
}

declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
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