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[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup #109417

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Merged
merged 3 commits into from
Sep 25, 2024
Merged

[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup #109417

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b3a4bff
[NFC] Switch a number of DenseMaps to SmallDenseMaps
jmorse Sep 19, 2024
1163e20
Publicise and scatter uses of InstrEmitters vreg-map-type
jmorse Sep 23, 2024
1e07934
clang-format a bit
jmorse Sep 23, 2024
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2 changes: 1 addition & 1 deletion llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
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Expand Up @@ -492,7 +492,7 @@ class MemoryDependenceResults {
const MemoryLocation &Loc, bool isLoad,
BasicBlock *BB,
SmallVectorImpl<NonLocalDepResult> &Result,
DenseMap<BasicBlock *, Value *> &Visited,
SmallDenseMap<BasicBlock *, Value *, 16> &Visited,
bool SkipFirstBlock = false,
bool IsIncomplete = false);
MemDepResult getNonLocalInfoForBlock(Instruction *QueryInst,
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/Analysis/SparsePropagation.h
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Expand Up @@ -89,7 +89,7 @@ template <class LatticeKey, class LatticeVal> class AbstractLatticeFunction {
/// \p ChangedValues.
virtual void
ComputeInstructionState(Instruction &I,
DenseMap<LatticeKey, LatticeVal> &ChangedValues,
SmallDenseMap<LatticeKey, LatticeVal, 16> &ChangedValues,
SparseSolver<LatticeKey, LatticeVal> &SS) = 0;

/// PrintLatticeVal - Render the given LatticeVal to the specified stream.
Expand Down Expand Up @@ -401,7 +401,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitPHINode(PHINode &PN) {
// computed from its incoming values. For example, SSI form stores its sigma
// functions as PHINodes with a single incoming value.
if (LatticeFunc->IsSpecialCasedPHI(&PN)) {
DenseMap<LatticeKey, LatticeVal> ChangedValues;
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
LatticeFunc->ComputeInstructionState(PN, ChangedValues, *this);
for (auto &ChangedValue : ChangedValues)
if (ChangedValue.second != LatticeFunc->getUntrackedVal())
Expand Down Expand Up @@ -456,7 +456,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitInst(Instruction &I) {

// Otherwise, ask the transfer function what the result is. If this is
// something that we care about, remember it.
DenseMap<LatticeKey, LatticeVal> ChangedValues;
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
LatticeFunc->ComputeInstructionState(I, ChangedValues, *this);
for (auto &ChangedValue : ChangedValues)
if (ChangedValue.second != LatticeFunc->getUntrackedVal())
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
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Expand Up @@ -888,7 +888,7 @@ void MemoryDependenceResults::getNonLocalPointerDependency(
// each block. Because of critical edges, we currently bail out if querying
// a block with multiple different pointers. This can happen during PHI
// translation.
DenseMap<BasicBlock *, Value *> Visited;
SmallDenseMap<BasicBlock *, Value *, 16> Visited;
if (getNonLocalPointerDepFromBB(QueryInst, Address, Loc, isLoad, FromBB,
Result, Visited, true))
return;
Expand Down Expand Up @@ -1038,7 +1038,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
Instruction *QueryInst, const PHITransAddr &Pointer,
const MemoryLocation &Loc, bool isLoad, BasicBlock *StartBB,
SmallVectorImpl<NonLocalDepResult> &Result,
DenseMap<BasicBlock *, Value *> &Visited, bool SkipFirstBlock,
SmallDenseMap<BasicBlock *, Value *, 16> &Visited, bool SkipFirstBlock,
bool IsIncomplete) {
// Look up the cached info for Pointer.
ValueIsLoadPair CacheKey(Pointer.getAddr(), isLoad);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Analysis/ScalarEvolution.cpp
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Expand Up @@ -2255,7 +2255,7 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op,
/// the common case where no interesting opportunities are present, and
/// is also used as a check to avoid infinite recursion.
static bool
CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M,
CollectAddOperandsWithScales(SmallDenseMap<const SCEV *, APInt, 16> &M,
SmallVectorImpl<const SCEV *> &NewOps,
APInt &AccumulatedConstant,
ArrayRef<const SCEV *> Ops, const APInt &Scale,
Expand Down Expand Up @@ -2753,7 +2753,7 @@ const SCEV *ScalarEvolution::getAddExpr(SmallVectorImpl<const SCEV *> &Ops,
// operands multiplied by constant values.
if (Idx < Ops.size() && isa<SCEVMulExpr>(Ops[Idx])) {
uint64_t BitWidth = getTypeSizeInBits(Ty);
DenseMap<const SCEV *, APInt> M;
SmallDenseMap<const SCEV *, APInt, 16> M;
SmallVector<const SCEV *, 8> NewOps;
APInt AccumulatedConstant(BitWidth, 0);
if (CollectAddOperandsWithScales(M, NewOps, AccumulatedConstant,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/CalcSpillWeights.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,

bool IsExiting = false;
std::set<CopyHint> CopyHints;
DenseMap<unsigned, float> Hint;
SmallDenseMap<unsigned, float, 8> Hint;
for (MachineRegisterInfo::reg_instr_nodbg_iterator
I = MRI.reg_instr_nodbg_begin(LI.reg()),
E = MRI.reg_instr_nodbg_end();
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/CodeGen/MachineLICM.cpp
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Expand Up @@ -239,7 +239,7 @@ namespace {

bool IsCheapInstruction(MachineInstr &MI) const;

bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
bool CanCauseHighRegPressure(const SmallDenseMap<unsigned, int> &Cost,
bool Cheap);

void UpdateBackTraceRegPressure(const MachineInstr *MI);
Expand All @@ -264,7 +264,7 @@ namespace {

void InitRegPressure(MachineBasicBlock *BB);

DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
SmallDenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
bool ConsiderSeen,
bool ConsiderUnseenAsDef);

Expand Down Expand Up @@ -977,10 +977,10 @@ void MachineLICMImpl::UpdateRegPressure(const MachineInstr *MI,
/// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
/// figure out which usages are live-ins.
/// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
DenseMap<unsigned, int>
SmallDenseMap<unsigned, int>
MachineLICMImpl::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
bool ConsiderUnseenAsDef) {
DenseMap<unsigned, int> Cost;
SmallDenseMap<unsigned, int> Cost;
if (MI->isImplicitDef())
return Cost;
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
Expand Down Expand Up @@ -1248,7 +1248,7 @@ bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
/// Visit BBs from header to current BB, check if hoisting an instruction of the
/// given cost matrix can cause high register pressure.
bool MachineLICMImpl::CanCauseHighRegPressure(
const DenseMap<unsigned, int> &Cost, bool CheapInstr) {
const SmallDenseMap<unsigned, int>& Cost, bool CheapInstr) {
for (const auto &RPIdAndCost : Cost) {
if (RPIdAndCost.second <= 0)
continue;
Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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Expand Up @@ -83,7 +83,7 @@ static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
/// implicit physical register output.
void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
Register SrcReg,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
Register VRBase;
if (SrcReg.isVirtual()) {
// Just use the input register directly!
Expand Down Expand Up @@ -187,7 +187,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
MachineInstrBuilder &MIB,
const MCInstrDesc &II,
bool IsClone, bool IsCloned,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");

Expand Down Expand Up @@ -266,7 +266,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
Register InstrEmitter::getVR(SDValue Op,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
Expand All @@ -280,7 +280,7 @@ Register InstrEmitter::getVR(SDValue Op,
return VReg;
}

DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
VRBaseMapType::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second;
}
Expand Down Expand Up @@ -318,7 +318,7 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
SDValue Op,
unsigned IIOpNum,
const MCInstrDesc *II,
DenseMap<SDValue, Register> &VRBaseMap,
VRBaseMapType &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned) {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue &&
Expand Down Expand Up @@ -399,7 +399,7 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
SDValue Op,
unsigned IIOpNum,
const MCInstrDesc *II,
DenseMap<SDValue, Register> &VRBaseMap,
VRBaseMapType &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned) {
if (Op.isMachineOpcode()) {
AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
Expand Down Expand Up @@ -500,7 +500,7 @@ Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void InstrEmitter::EmitSubregNode(SDNode *Node,
DenseMap<SDValue, Register> &VRBaseMap,
VRBaseMapType &VRBaseMap,
bool IsClone, bool IsCloned) {
Register VRBase;
unsigned Opc = Node->getMachineOpcode();
Expand Down Expand Up @@ -634,7 +634,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
///
void
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
Register VReg = getVR(Node->getOperand(0), VRBaseMap);

// Create the new VReg in the destination class and emit a copy.
Expand All @@ -654,7 +654,7 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
///
void InstrEmitter::EmitRegSequence(SDNode *Node,
DenseMap<SDValue, Register> &VRBaseMap,
VRBaseMapType &VRBaseMap,
bool IsClone, bool IsCloned) {
unsigned DstRCIdx = Node->getConstantOperandVal(0);
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
Expand Down Expand Up @@ -703,7 +703,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
///
MachineInstr *
InstrEmitter::EmitDbgValue(SDDbgValue *SD,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
DebugLoc DL = SD->getDebugLoc();
assert(cast<DILocalVariable>(SD->getVariable())
->isValidLocationForIntrinsic(DL) &&
Expand Down Expand Up @@ -755,7 +755,7 @@ MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
void InstrEmitter::AddDbgValueLocationOps(
MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
ArrayRef<SDDbgOperand> LocationOps,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
for (const SDDbgOperand &Op : LocationOps) {
switch (Op.getKind()) {
case SDDbgOperand::FRAMEIX:
Expand Down Expand Up @@ -786,7 +786,7 @@ void InstrEmitter::AddDbgValueLocationOps(

MachineInstr *
InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
const DIExpression *Expr = (DIExpression *)SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
Expand Down Expand Up @@ -862,7 +862,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
// Look up the corresponding VReg for the given SDNode, if any.
SDNode *Node = DbgOperand.getSDNode();
SDValue Op = SDValue(Node, DbgOperand.getResNo());
DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
VRBaseMapType::iterator I = VRBaseMap.find(Op);
// No VReg -> produce a DBG_VALUE $noreg instead.
if (I == VRBaseMap.end())
break;
Expand Down Expand Up @@ -928,7 +928,7 @@ MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {

MachineInstr *
InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
DIExpression *Expr = SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
Expand All @@ -944,7 +944,7 @@ InstrEmitter::EmitDbgValueList(SDDbgValue *SD,

MachineInstr *
InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
DIExpression *Expr = SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
Expand Down Expand Up @@ -996,7 +996,7 @@ InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
///
void InstrEmitter::
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
unsigned Opc = Node->getMachineOpcode();

// Handle subreg insert/extract specially
Expand Down Expand Up @@ -1238,7 +1238,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
/// needed dependencies.
void InstrEmitter::
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, Register> &VRBaseMap) {
VRBaseMapType &VRBaseMap) {
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
Expand Down
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