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[X86][CodeGen] Add base atan2 intrinsic lowering (p4) #110760

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Merged
merged 3 commits into from
Oct 16, 2024
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[X86][CodeGen] Add base atan2 intrinsic lowering (p4) #110760

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e6027f7
[X86][CodeGen] Add base atan2 intrinsic lowering (p4)
tex3d Sep 15, 2024
08d8192
Remove GlobalISel changes not needed yet
tex3d Oct 10, 2024
ee710fb
Remove accidental UTC_ARGS addition to update_llc_test_checks
tex3d Oct 14, 2024
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3 changes: 3 additions & 0 deletions llvm/include/llvm/CodeGen/BasicTTIImpl.h
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Expand Up @@ -1998,6 +1998,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
case Intrinsic::atan:
ISD = ISD::FATAN;
break;
case Intrinsic::atan2:
ISD = ISD::FATAN2;
break;
case Intrinsic::sinh:
ISD = ISD::FSINH;
break;
Expand Down
3 changes: 3 additions & 0 deletions llvm/include/llvm/CodeGen/ISDOpcodes.h
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Expand Up @@ -425,6 +425,7 @@ enum NodeType {
STRICT_FASIN,
STRICT_FACOS,
STRICT_FATAN,
STRICT_FATAN2,
STRICT_FSINH,
STRICT_FCOSH,
STRICT_FTANH,
Expand Down Expand Up @@ -994,6 +995,8 @@ enum NodeType {
FPOWI,
/// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
FLDEXP,
/// FATAN2 - atan2, inspired by libm.
FATAN2,

/// FFREXP - frexp, extract fractional and exponent component of a
/// floating-point value. Returns the two components as separate return
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/IR/ConstrainedOps.def
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Expand Up @@ -72,6 +72,7 @@ CMP_INSTRUCTION(FCmp, 2, 0, experimental_constrained_fcmps, FSETCCS
DAG_FUNCTION(acos, 1, 1, experimental_constrained_acos, FACOS)
DAG_FUNCTION(asin, 1, 1, experimental_constrained_asin, FASIN)
DAG_FUNCTION(atan, 1, 1, experimental_constrained_atan, FATAN)
DAG_FUNCTION(atan2, 2, 1, experimental_constrained_atan2, FATAN2)
DAG_FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
DAG_FUNCTION(cosh, 1, 1, experimental_constrained_cosh, FCOSH)
Expand Down
5 changes: 5 additions & 0 deletions llvm/include/llvm/IR/Intrinsics.td
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Expand Up @@ -1235,6 +1235,11 @@ let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn, IntrStrictFP] in
[ LLVMMatchType<0>,
llvm_metadata_ty,
llvm_metadata_ty ]>;
def int_experimental_constrained_atan2 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
[ LLVMMatchType<0>,
LLVMMatchType<0>,
llvm_metadata_ty,
llvm_metadata_ty ]>;
def int_experimental_constrained_sin : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
[ LLVMMatchType<0>,
llvm_metadata_ty,
Expand Down
5 changes: 5 additions & 0 deletions llvm/include/llvm/IR/RuntimeLibcalls.def
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Expand Up @@ -232,6 +232,11 @@ HANDLE_LIBCALL(ATAN_F64, "atan")
HANDLE_LIBCALL(ATAN_F80, "atanl")
HANDLE_LIBCALL(ATAN_F128,"atanl")
HANDLE_LIBCALL(ATAN_PPCF128, "atanl")
HANDLE_LIBCALL(ATAN2_F32, "atan2f")
HANDLE_LIBCALL(ATAN2_F64, "atan2")
HANDLE_LIBCALL(ATAN2_F80, "atan2l")
HANDLE_LIBCALL(ATAN2_F128,"atan2l")
HANDLE_LIBCALL(ATAN2_PPCF128, "atan2l")
HANDLE_LIBCALL(SINCOS_F32, nullptr)
HANDLE_LIBCALL(SINCOS_F64, nullptr)
HANDLE_LIBCALL(SINCOS_F80, nullptr)
Expand Down
6 changes: 6 additions & 0 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
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Expand Up @@ -534,6 +534,7 @@ def ftan : SDNode<"ISD::FTAN" , SDTFPUnaryOp>;
def fasin : SDNode<"ISD::FASIN" , SDTFPUnaryOp>;
def facos : SDNode<"ISD::FACOS" , SDTFPUnaryOp>;
def fatan : SDNode<"ISD::FATAN" , SDTFPUnaryOp>;
def fatan2 : SDNode<"ISD::FATAN2" , SDTFPBinOp>;
def fsinh : SDNode<"ISD::FSINH" , SDTFPUnaryOp>;
def fcosh : SDNode<"ISD::FCOSH" , SDTFPUnaryOp>;
def ftanh : SDNode<"ISD::FTANH" , SDTFPUnaryOp>;
Expand Down Expand Up @@ -602,6 +603,8 @@ def strict_facos : SDNode<"ISD::STRICT_FACOS",
SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fatan : SDNode<"ISD::STRICT_FATAN",
SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fatan2 : SDNode<"ISD::STRICT_FATAN2",
SDTFPBinOp, [SDNPHasChain]>;
def strict_fsinh : SDNode<"ISD::STRICT_FSINH",
SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fcosh : SDNode<"ISD::STRICT_FCOSH",
Expand Down Expand Up @@ -1588,6 +1591,9 @@ def any_facos : PatFrags<(ops node:$src),
def any_fatan : PatFrags<(ops node:$src),
[(strict_fatan node:$src),
(fatan node:$src)]>;
def any_fatan2 : PatFrags<(ops node:$src1, node:$src2),
[(strict_fatan2 node:$src1, node:$src2),
(fatan2 node:$src1, node:$src2)]>;
def any_fsinh : PatFrags<(ops node:$src),
[(strict_fsinh node:$src),
(fsinh node:$src)]>;
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Expand Up @@ -4600,6 +4600,11 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
ExpandFPLibCall(Node, RTLIB::ATAN_F32, RTLIB::ATAN_F64, RTLIB::ATAN_F80,
RTLIB::ATAN_F128, RTLIB::ATAN_PPCF128, Results);
break;
case ISD::FATAN2:
case ISD::STRICT_FATAN2:
ExpandFPLibCall(Node, RTLIB::ATAN2_F32, RTLIB::ATAN2_F64, RTLIB::ATAN2_F80,
RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128, Results);
break;
case ISD::FSINH:
case ISD::STRICT_FSINH:
ExpandFPLibCall(Node, RTLIB::SINH_F32, RTLIB::SINH_F64, RTLIB::SINH_F80,
Expand Down Expand Up @@ -5486,6 +5491,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
case ISD::FMINIMUMNUM:
case ISD::FMAXIMUMNUM:
case ISD::FPOW:
case ISD::FATAN2:
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
Expand All @@ -5502,6 +5508,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
case ISD::STRICT_FMAXNUM:
case ISD::STRICT_FREM:
case ISD::STRICT_FPOW:
case ISD::STRICT_FATAN2:
Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
{Node->getOperand(0), Node->getOperand(1)});
Tmp2 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
Expand Down
22 changes: 22 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -84,6 +84,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FASIN: R = SoftenFloatRes_FASIN(N); break;
case ISD::STRICT_FATAN:
case ISD::FATAN: R = SoftenFloatRes_FATAN(N); break;
case ISD::STRICT_FATAN2:
case ISD::FATAN2: R = SoftenFloatRes_FATAN2(N); break;
case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break;
case ISD::STRICT_FCEIL:
case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
Expand Down Expand Up @@ -366,6 +368,13 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FATAN(SDNode *N) {
RTLIB::ATAN_F80, RTLIB::ATAN_F128, RTLIB::ATAN_PPCF128));
}

SDValue DAGTypeLegalizer::SoftenFloatRes_FATAN2(SDNode *N) {
return SoftenFloatRes_Binary(
N,
GetFPLibCall(N->getValueType(0), RTLIB::ATAN2_F32, RTLIB::ATAN2_F64,
RTLIB::ATAN2_F80, RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128));
}

SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
RTLIB::CBRT_F32,
Expand Down Expand Up @@ -1430,6 +1439,8 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FASIN: ExpandFloatRes_FASIN(N, Lo, Hi); break;
case ISD::STRICT_FATAN:
case ISD::FATAN: ExpandFloatRes_FATAN(N, Lo, Hi); break;
case ISD::STRICT_FATAN2:
case ISD::FATAN2: ExpandFloatRes_FATAN2(N, Lo, Hi); break;
case ISD::FCBRT: ExpandFloatRes_FCBRT(N, Lo, Hi); break;
case ISD::STRICT_FCEIL:
case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
Expand Down Expand Up @@ -1631,6 +1642,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FATAN(SDNode *N, SDValue &Lo,
Lo, Hi);
}

void DAGTypeLegalizer::ExpandFloatRes_FATAN2(SDNode *N, SDValue &Lo,
SDValue &Hi) {
ExpandFloatRes_Binary(N,
GetFPLibCall(N->getValueType(0), RTLIB::ATAN2_F32,
RTLIB::ATAN2_F64, RTLIB::ATAN2_F80,
RTLIB::ATAN2_F128, RTLIB::ATAN2_PPCF128),
Lo, Hi);
}

void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CBRT_F32,
Expand Down Expand Up @@ -2673,6 +2693,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FMINNUM_IEEE:
case ISD::FMUL:
case ISD::FPOW:
case ISD::FATAN2:
case ISD::FREM:
case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;

Expand Down Expand Up @@ -3115,6 +3136,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FMINNUM:
case ISD::FMUL:
case ISD::FPOW:
case ISD::FATAN2:
case ISD::FREM:
case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break;

Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -567,6 +567,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_FACOS(SDNode *N);
SDValue SoftenFloatRes_FASIN(SDNode *N);
SDValue SoftenFloatRes_FATAN(SDNode *N);
SDValue SoftenFloatRes_FATAN2(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
SDValue SoftenFloatRes_FMINIMUMNUM(SDNode *N);
Expand Down Expand Up @@ -661,6 +662,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandFloatRes_FACOS (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FASIN (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FATAN (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FATAN2 (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMINIMUMNUM(SDNode *N, SDValue &Lo, SDValue &Hi);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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Expand Up @@ -410,6 +410,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FASIN:
case ISD::FACOS:
case ISD::FATAN:
case ISD::FATAN2:
case ISD::FSINH:
case ISD::FCOSH:
case ISD::FTANH:
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Expand Up @@ -164,6 +164,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::USHLSAT:

case ISD::FPOW:
case ISD::FATAN2:
case ISD::FREM:
case ISD::FSUB:
case ISD::MUL:
Expand Down Expand Up @@ -1293,6 +1294,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UDIV: case ISD::VP_UDIV:
case ISD::FDIV: case ISD::VP_FDIV:
case ISD::FPOW:
case ISD::FATAN2:
case ISD::AND: case ISD::VP_AND:
case ISD::OR: case ISD::VP_OR:
case ISD::XOR: case ISD::VP_XOR:
Expand Down Expand Up @@ -4581,6 +4583,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
break;

case ISD::FPOW:
case ISD::FATAN2:
case ISD::FREM:
if (unrollExpandedOp())
break;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -5471,6 +5471,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
case ISD::FASIN:
case ISD::FACOS:
case ISD::FATAN:
case ISD::FATAN2:
case ISD::FSINH:
case ISD::FCOSH:
case ISD::FTANH:
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -6861,6 +6861,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
getValue(I.getArgOperand(0)), Flags));
return;
}
case Intrinsic::atan2:
setValue(&I, DAG.getNode(ISD::FATAN2, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0)),
getValue(I.getArgOperand(1)), Flags));
return;
case Intrinsic::lround:
case Intrinsic::llround:
case Intrinsic::lrint:
Expand Down Expand Up @@ -9353,6 +9359,12 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitUnaryFloatCall(I, ISD::FATAN))
return;
break;
case LibFunc_atan2:
case LibFunc_atan2f:
case LibFunc_atan2l:
if (visitBinaryFloatCall(I, ISD::FATAN2))
return;
break;
case LibFunc_sinh:
case LibFunc_sinhf:
case LibFunc_sinhl:
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
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Expand Up @@ -227,6 +227,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::STRICT_FACOS: return "strict_facos";
case ISD::FATAN: return "fatan";
case ISD::STRICT_FATAN: return "strict_fatan";
case ISD::FATAN2: return "fatan2";
case ISD::STRICT_FATAN2: return "strict_fatan2";
case ISD::FSINH: return "fsinh";
case ISD::STRICT_FSINH: return "strict_fsinh";
case ISD::FCOSH: return "fcosh";
Expand Down
7 changes: 4 additions & 3 deletions llvm/lib/CodeGen/TargetLoweringBase.cpp
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Expand Up @@ -783,7 +783,7 @@ void TargetLoweringBase::initActions() {
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
ISD::FCOSH, ISD::FSINH, ISD::FTANH},
ISD::FCOSH, ISD::FSINH, ISD::FTANH, ISD::FATAN2},
VT, Expand);

// Constrained floating-point operations default to expand.
Expand Down Expand Up @@ -842,15 +842,16 @@ void TargetLoweringBase::initActions() {
ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH,
ISD::FATAN2},
{MVT::f32, MVT::f64, MVT::f128}, Expand);

// FIXME: Query RuntimeLibCalls to make the decision.
setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
{MVT::f32, MVT::f64, MVT::f128}, LibCall);

setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
ISD::FSINH, ISD::FTANH},
ISD::FSINH, ISD::FTANH, ISD::FATAN2},
MVT::f16, Promote);
// Default ISD::TRAP to expand (which turns it into abort).
setOperationAction(ISD::TRAP, MVT::Other, Expand);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/IR/RuntimeLibcalls.cpp
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Expand Up @@ -49,6 +49,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
setLibcallName(RTLIB::ASIN_F128, "asinf128");
setLibcallName(RTLIB::ACOS_F128, "acosf128");
setLibcallName(RTLIB::ATAN_F128, "atanf128");
setLibcallName(RTLIB::ATAN2_F128, "atan2f128");
setLibcallName(RTLIB::SINH_F128, "sinhf128");
setLibcallName(RTLIB::COSH_F128, "coshf128");
setLibcallName(RTLIB::TANH_F128, "tanhf128");
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -858,6 +858,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FASIN , MVT::f80, Expand);
setOperationAction(ISD::FACOS , MVT::f80, Expand);
setOperationAction(ISD::FATAN , MVT::f80, Expand);
setOperationAction(ISD::FATAN2 , MVT::f80, Expand);
setOperationAction(ISD::FSINH , MVT::f80, Expand);
setOperationAction(ISD::FCOSH , MVT::f80, Expand);
setOperationAction(ISD::FTANH , MVT::f80, Expand);
Expand Down Expand Up @@ -2562,6 +2563,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
{ISD::FACOS, ISD::STRICT_FACOS,
ISD::FASIN, ISD::STRICT_FASIN,
ISD::FATAN, ISD::STRICT_FATAN,
ISD::FATAN2, ISD::STRICT_FATAN2,
ISD::FCEIL, ISD::STRICT_FCEIL,
ISD::FCOS, ISD::STRICT_FCOS,
ISD::FCOSH, ISD::STRICT_FCOSH,
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/Assembler/fp-intrinsics-attr.ll
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Expand Up @@ -105,6 +105,11 @@ define void @func(double %a, double %b, double %c, i32 %i) strictfp {
metadata !"round.dynamic",
metadata !"fpexcept.strict")

%atan2 = call double @llvm.experimental.constrained.atan2.f64(
double %a, double %b,
metadata !"round.dynamic",
metadata !"fpexcept.strict")

%cosh = call double @llvm.experimental.constrained.cosh.f64(
double %a,
metadata !"round.dynamic",
Expand Down Expand Up @@ -291,6 +296,9 @@ declare double @llvm.experimental.constrained.acos.f64(double, metadata, metadat
declare double @llvm.experimental.constrained.atan.f64(double, metadata, metadata)
; CHECK: @llvm.experimental.constrained.atan.f64({{.*}}) #[[ATTR1]]

declare double @llvm.experimental.constrained.atan2.f64(double, double, metadata, metadata)
; CHECK: @llvm.experimental.constrained.atan2.f64({{.*}}) #[[ATTR1]]

declare double @llvm.experimental.constrained.sinh.f64(double, metadata, metadata)
; CHECK: @llvm.experimental.constrained.sinh.f64({{.*}}) #[[ATTR1]]

Expand Down
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