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[GISel] Don't preserve NSW flag when converting G_MUL of INT_MIN to G_SHL. #111230

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merged 1 commit into from
Oct 5, 2024

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@topperc topperc commented Oct 5, 2024

mul and shl have different meanings for the nsw flag. We need to drop it when converting a multiply by the minimum negative value.

…_SHL.

mul and shl have different meanings for the nsw flag. We need to
drop it when multiplying by minimum negative value.
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llvmbot commented Oct 5, 2024

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-aarch64

Author: Craig Topper (topperc)

Changes

mul and shl have different meanings for the nsw flag. We need to drop it when converting a multiply by the minimum negative value.


Full diff: https://github.com/llvm/llvm-project/pull/111230.diff

2 Files Affected:

  • (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+2)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir (+48)
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c279289f9161bf..14e94d48bf8362 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2036,6 +2036,8 @@ void CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
   Observer.changingInstr(MI);
   MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL));
   MI.getOperand(2).setReg(ShiftCst.getReg(0));
+  if (ShiftVal == ShiftTy.getScalarSizeInBits() - 1)
+    MI.clearFlag(MachineInstr::MIFlag::NoSWrap);
   Observer.changedInstr(MI);
 }
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
index 068f8e3beb9ed4..71eaf80f53ba4c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
@@ -96,3 +96,51 @@ body:             |
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit-def $x0
 ...
+---
+name:            mul_to_shl_16_nuw_nsw
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: mul_to_shl_16_nuw_nsw
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = nuw nsw G_SHL [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: $x0 = COPY [[SHL]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit-def $x0
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = G_CONSTANT i64 16
+    %2:_(s64) = nuw nsw G_MUL %0, %1(s64)
+    $x0 = COPY %2(s64)
+    RET_ReallyLR implicit-def $x0
+...
+---
+name:            mul_to_shl_int_min_nuw_nsw
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: mul_to_shl_int_min_nuw_nsw
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = nuw G_SHL [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: $x0 = COPY [[SHL]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit-def $x0
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = G_CONSTANT i64 -9223372036854775808
+    %2:_(s64) = nuw nsw G_MUL %0, %1(s64)
+    $x0 = COPY %2(s64)
+    RET_ReallyLR implicit-def $x0
+...

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LGTM

@topperc topperc merged commit 20e37f0 into llvm:main Oct 5, 2024
12 checks passed
@topperc topperc deleted the pr/gisel-mul-shift-flag branch October 5, 2024 17:28
Kyvangka1610 added a commit to Kyvangka1610/llvm-project that referenced this pull request Oct 6, 2024
* commit 'FETCH_HEAD':
  [X86] combineAndLoadToBZHI - don't do an return early return if we fail to match a load
  [X86] replace-load-and-with-bzhi.ll - add commuted test cases to show failure to fold
  [X86] replace-load-and-with-bzhi.ll - cleanup check-prefixes to use X86/X64 for 32/64-bit targets
  [ExecutionEngine] Avoid repeated hash lookups (NFC) (llvm#111275)
  [ByteCode] Avoid repeated hash lookups (NFC) (llvm#111273)
  [StaticAnalyzer] Avoid repeated hash lookups (NFC) (llvm#111272)
  [CodeGen] Avoid repeated hash lookups (NFC) (llvm#111274)
  [RISCV] Simplify fixed-vector-fp.ll run lines. NFC
  [libc++][format][1/3] Adds more benchmarks. (llvm#101803)
  [X86] combineOrXorWithSETCC - avoid duplicate SDLoc/operands code. NFC.
  [X86] convertIntLogicToFPLogic - avoid duplicate SDLoc/operands code. NFC.
  [libc] Clean up some include in `libc`. (llvm#110980)
  [X86] combineBitOpWithPACK - avoid duplicate SDLoc/operands code. NFC.
  [X86] combineBitOpWithMOVMSK - avoid duplicate SDLoc/operands code. NFC.
  [X86] combineBitOpWithShift - avoid duplicate SDLoc/operands code. NFC.
  [x86] combineMul - use computeKnownBits directly to find MUL_IMM constant splat.
  [X86] combineSubABS - avoid duplicate SDLoc. NFC.
  [ValueTypes][RISCV] Add v1bf16 type (llvm#111112)
  [VPlan] Add additional FOR hoisting test.
  [clang-tidy] Create bugprone-bitwise-pointer-cast check (llvm#108083)
  [InstCombine] Canonicalize more geps with constant gep bases and constant offsets. (llvm#110033)
  [LV] Honor uniform-after-vectorization in setVectorizedCallDecision.
  [ELF] Pass Ctx & to Arch/
  [ELF] Pass Ctx & to Arch/
  [libc++] Fix a typo (llvm#111239)
  [X86] For minsize memset/memcpy, use byte or double-word accesses (llvm#87003)
  [RISCV] Unify RVBShift_ri and RVBShiftW_ri with Shift_ri and ShiftW_ri. NFC (llvm#111263)
  Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (llvm#110714)" (llvm#111059)"
  [libc] Add missing include to __support/StringUtil/tables/stdc_errors.h. (llvm#111271)
  [libc] remove errno.h includes (llvm#110934)
  [NFC][rtsan] Update docs to include [[clang::blocking]] (llvm#111249)
  [RISCV] Give ZEXT_H_RV32 and ZEXT_H_RV64 R-type format to match PACK. NFC
  [mlir][SPIRV] Fix build (2) (llvm#111265)
  [mlir][SPIRV] Fix build error (llvm#111264)
  [mlir][NFC] Mark type converter in `populate...` functions as `const` (llvm#111250)
  [Basic] Avoid repeated hash lookups (NFC) (llvm#111228)
  [RISCV] Use THShift_ri class instead of RVBShift_ri for TH_TST instruction. NFC
  [VPlan] Only generate first lane for VPPredInstPHI if no others used.
  [ELF] Don't call getPPC64TargetInfo outside Driver. NFC
  [GISel] Don't preserve NSW flag when converting G_MUL of INT_MIN to G_SHL. (llvm#111230)
  [APInt] Slightly simplify APInt::ashrSlowCase. NFC (llvm#111220)
  [Sema] Avoid repeated hash lookups (NFC) (llvm#111227)
  [Affine] Avoid repeated hash lookups (NFC) (llvm#111226)
  [Driver] Avoid repeated hash lookups (NFC) (llvm#111225)
  [clang][test] Remove a broken bytecode test
  [ELF] Pass Ctx &
  [ELF] Pass Ctx & to Relocations

Signed-off-by: kyvangka1610 <[email protected]>
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