[X86][MC] Support instructions of MSR_IMM

llvm/docs/ReleaseNotes.md

@@ -196,6 +196,8 @@ Changes to the X86 Backend
 
 * Support ISA of `AVX10.2-256` and `AVX10.2-512`.
 
+* Support ISA of `MSR_IMM`.
+
 Changes to the OCaml bindings
 -----------------------------
 

llvm/lib/Target/X86/X86InstrSystem.td

@@ -466,7 +466,10 @@ multiclass Urdwrmsr<Map rrmap, string suffix> {
                                 "urdmsr\t{$imm, $dst|$dst, $imm}",
                                 [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
                            T_MAP7, VEX, XD, NoCD8;
-}
+    def RDMSRri#suffix  : Ii32<0xf6, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+                                "rdmsr\t{$imm, $dst|$dst, $imm}", []>,
+                           T_MAP7, VEX, XD, NoCD8;
+  }
   let mayStore = 1 in {
     let OpMap = rrmap in
     def UWRMSRrr#suffix  : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
@@ -476,6 +479,9 @@ multiclass Urdwrmsr<Map rrmap, string suffix> {
                                 "uwrmsr\t{$src, $imm|$imm, $src}",
                                 [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
                            T_MAP7, VEX, XS, NoCD8;
+    def WRMSRNSir#suffix  : Ii32<0xf6, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+                                "wrmsrns\t{$src, $imm|$imm, $src}",
+                                []>, T_MAP7, VEX, XS, NoCD8;
   }
 }
 

llvm/test/MC/Disassembler/X86/apx/msr-imm.txt

@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   rdmsr $123, %r9
+# INTEL: rdmsr r9, 123
+0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT:   rdmsr $123, %r19
+# INTEL: rdmsr r19, 123
+0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT:   wrmsrns %r9, $123
+# INTEL: wrmsrns 123, r9
+0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT:   wrmsrns %r19, $123
+# INTEL: wrmsrns 123, r19
+0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00

llvm/test/MC/Disassembler/X86/msrimm-64.txt

@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   rdmsr $123, %r9
+# INTEL: rdmsr r9, 123
+0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT:   wrmsrns %r9, $123
+# INTEL: wrmsrns 123, r9
+0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00

llvm/test/MC/X86/apx/msrimm-att.s

@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+
+## rdmsr
+
+// CHECK: {evex} rdmsr $123, %r9
+// CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+          {evex} rdmsr $123, %r9
+
+// CHECK: rdmsr $123, %r19
+// CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+          rdmsr $123, %r19
+
+## wrmsrns
+
+# CHECK: {evex}	wrmsrns %r9, $123
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+         {evex}	wrmsrns %r9, $123
+
+# CHECK: wrmsrns %r19, $123
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+         wrmsrns %r19, $123

llvm/test/MC/X86/apx/msrimm-intel.s

@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## urdmsr
+
+# CHECK: {evex}	rdmsr r9, 123
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+         {evex}	rdmsr r9, 123
+
+# CHECK: rdmsr r19, 123
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+         rdmsr r19, 123
+
+## uwrmsr
+
+# CHECK: {evex}	wrmsrns 123, r9
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+         {evex}	wrmsrns 123, r9
+
+# CHECK: wrmsrns 123, r19
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+         wrmsrns 123, r19

llvm/test/MC/X86/msrimm-64-att.s

@@ -0,0 +1,10 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: rdmsr $123, %r9
+// CHECK: encoding: [0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+          rdmsr $123, %r9
+
+// CHECK: wrmsrns %r9, $123
+// CHECK: encoding: [0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+          wrmsrns %r9, $123
+

llvm/test/MC/X86/msrimm-64-intel.s

@@ -0,0 +1,10 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: rdmsr r9, 123
+// CHECK: encoding: [0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+          rdmsr r9, 123
+
+// CHECK: wrmsrns 123, r9
+// CHECK: encoding: [0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+          wrmsrns 123, r9
+