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[FMV][AArch64] Remove features which can be expressed as a combination of others. #113580

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Merged
merged 5 commits into from
Oct 30, 2024
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[FMV][AArch64] Remove features which can be expressed as a combination of others. #113580

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[FMV][AArch64] Remove features which can be expressed as a combinatio…
labrinea Oct 24, 2024
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clang format
labrinea Oct 24, 2024
586b092
Merge branch 'main' into fmv-remove-combined-features
labrinea Oct 28, 2024
add99fc
Changes from last revision:
labrinea Oct 29, 2024
7bdd578
Merge branch 'main' into fmv-remove-combined-features
labrinea Oct 29, 2024
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11 changes: 0 additions & 11 deletions clang/test/CodeGen/aarch64-fmv-dependencies.c
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Expand Up @@ -135,15 +135,6 @@ __attribute__((target_version("ssbs"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] {
__attribute__((target_version("sve"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] {
__attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] {
__attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] {
__attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] {
__attribute__((target_version("sve2"))) int fmv(void) { return 0; }

Expand Down Expand Up @@ -209,8 +200,6 @@ int caller() {
// CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a"
// CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
// CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
Expand Down
20 changes: 10 additions & 10 deletions clang/test/CodeGen/attr-target-version.c
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Expand Up @@ -27,11 +27,11 @@ int foo() {
inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; }
inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; }
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; }
inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
Expand Down Expand Up @@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 8
Expand Down Expand Up @@ -708,7 +708,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve
// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 4
Expand Down Expand Up @@ -837,20 +837,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
// CHECK: resolver_else12:
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1207959552
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1207959552
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
// CHECK: resolver_return13:
// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve
// CHECK: resolver_else14:
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
// CHECK: resolver_return15:
// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16
// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16
// CHECK: resolver_else16:
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
Expand Down
4 changes: 2 additions & 2 deletions clang/test/Sema/attr-target-clones-aarch64.c
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Expand Up @@ -7,7 +7,7 @@ void __attribute__((target_clones("default+sha3"))) warn1(void);

// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
// expected-note@+1 {{conflicting attribute is here}}
void __attribute__((target_version("sve-bf16"), target_clones("sme+memtag"))) not_compat(void);
void __attribute__((target_version("sve"), target_clones("sme+memtag"))) not_compat(void);

int redecl(void);
int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; }
Expand Down Expand Up @@ -78,4 +78,4 @@ int useage(void) {
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; }
// expected-error@+1 {{'main' cannot be a multiversioned function}}
int __attribute__((target_clones("sve-i8mm"))) main() { return 1; }
int __attribute__((target_clones("i8mm"))) main() { return 1; }
4 changes: 2 additions & 2 deletions clang/test/SemaCXX/attr-target-version.cpp
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Expand Up @@ -49,7 +49,7 @@ double __attribute__((target_version("rcpc"))) diff_type1(void);

auto __attribute__((target_version("rcpc2"))) diff_type2(void) -> int { return 1; }
//expected-error@+1 {{multiversioned function declaration has a different return type}}
auto __attribute__((target_version("sve-bf16"))) diff_type2(void) -> long { return (long)1; }
auto __attribute__((target_version("bf16"))) diff_type2(void) -> long { return (long)1; }

int __attribute__((target_version("fp16fml"))) diff_type3(void) noexcept(false) { return 1; }
//expected-error@+2 {{exception specification in declaration does not match previous declaration}}
Expand All @@ -75,7 +75,7 @@ auto __attribute__((target_version("dpb2"))) ret3(void) -> int { return 1; }
class Cls {
__attribute__((target_version("rng"))) Cls();
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support constructors}}
__attribute__((target_version("sve-i8mm"))) ~Cls();
__attribute__((target_version("i8mm"))) ~Cls();
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support destructors}}

Cls &__attribute__((target_version("f32mm"))) operator=(const Cls &) = default;
Expand Down
6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
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Expand Up @@ -53,9 +53,9 @@ enum CPUFeatures {
FEAT_EBF16,
FEAT_RPRES,
FEAT_SVE,
FEAT_SVE_BF16,
FEAT_SVE_EBF16,
FEAT_SVE_I8MM,
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy
FEAT_SVE_F32MM,
FEAT_SVE_F64MM,
FEAT_SVE2,
Expand Down
6 changes: 0 additions & 6 deletions compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
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Expand Up @@ -65,14 +65,10 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_I8MM);
if (hwcap2 & HWCAP2_EBF16)
setCPUFeature(FEAT_EBF16);
if (hwcap2 & HWCAP2_SVE_EBF16)
setCPUFeature(FEAT_SVE_EBF16);
if (hwcap2 & HWCAP2_DGH)
setCPUFeature(FEAT_DGH);
if (hwcap2 & HWCAP2_FRINT)
setCPUFeature(FEAT_FRINTTS);
if (hwcap2 & HWCAP2_SVEI8MM)
setCPUFeature(FEAT_SVE_I8MM);
if (hwcap2 & HWCAP2_SVEF32MM)
setCPUFeature(FEAT_SVE_F32MM);
if (hwcap2 & HWCAP2_SVEF64MM)
Expand Down Expand Up @@ -119,8 +115,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_RCPC3);
if (hwcap2 & HWCAP2_BF16)
setCPUFeature(FEAT_BF16);
if (hwcap2 & HWCAP2_SVEBF16)
setCPUFeature(FEAT_SVE_BF16);
if (hwcap & HWCAP_SVE)
setCPUFeature(FEAT_SVE);
if (hwcap2 & HWCAP2_SVE2)
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
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Expand Up @@ -53,9 +53,9 @@ enum CPUFeatures {
FEAT_EBF16,
FEAT_RPRES,
FEAT_SVE,
FEAT_SVE_BF16,
FEAT_SVE_EBF16,
FEAT_SVE_I8MM,
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy
FEAT_SVE_F32MM,
FEAT_SVE_F64MM,
FEAT_SVE2,
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/AArch64/AArch64FMV.td
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Expand Up @@ -81,9 +81,6 @@ def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>;
def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
Expand Down
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