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[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. #114186

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Merged
merged 2 commits into from
Oct 30, 2024
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[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. #114186

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[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might …
topperc Oct 30, 2024
6c7ec35
Merge remote-tracking branch 'origin/main' into pr/rounding-post-isel
topperc Oct 30, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2623,6 +2623,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}

if (int Idx = RISCVII::getFRMOpNum(Desc);
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This is checking the pseudo form, is there any way that we can add an additional assert which checks the pseudo against the underlying instruction? The underlying instruction needs to have the use of FRM too doesn't it?

(Possible follow up)

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The underlying instruction should have it but I don't think anything breaks if it doesn't.

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Wouldn't a disassembly use case be wrong if we didn't have the implicit use?

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It doesn't affect the printing of the instruction so the main use of disassembly wouldn't notice.

Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN &&
!MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) {
ErrInfo = "dynamic rounding mode should read FRM";
return false;
}

return true;
}

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17 changes: 8 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -6479,7 +6479,7 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
}

Expand Down Expand Up @@ -6512,7 +6512,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
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It doesn't look like we have support for this today, but maybe we should add a target hook for this instead? Having the post ISEL hook driven by tablgen (as opposed to a query on the underlying instruction), seems error prone. Another idea might be a target specific consistency check before emission so at least we know at build time that pseudos and instructions are in sync?

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I was planning to move the hasPostISelHook=1 into the base class where has HasRoundMode is set. The flag should be set anytime HasRoundMode==1 && UsesVXRM=0.

defm PseudoVFSQRT : VPseudoVSQR_V_RM;

//===----------------------------------------------------------------------===//
Expand All @@ -6524,7 +6524,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
defm PseudoVFREC7 : VPseudoVRCP_V_RM;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -6636,9 +6636,10 @@ defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;

let hasSideEffects = 0, hasPostISelHook = 1 in
let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
}

defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
} // mayRaiseFPException = true
Expand Down Expand Up @@ -6674,8 +6675,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true,
hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
Expand All @@ -6687,9 +6687,8 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let IsRVVWideningReduction = 1,
hasSideEffects = 0,
mayRaiseFPException = true in {
let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true,
hasPostISelHook = 1 in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
}
Expand Down
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