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[RISCV] Remove duplicate vector conversion pseudos. #114287

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Merged
merged 5 commits into from
Oct 30, 2024
Merged

[RISCV] Remove duplicate vector conversion pseudos. #114287

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4827265
[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might …
topperc Oct 30, 2024
6c7ec35
Merge remote-tracking branch 'origin/main' into pr/rounding-post-isel
topperc Oct 30, 2024
529a555
Merge remote-tracking branch 'origin/main' into pr/rounding-mode-sink
topperc Oct 30, 2024
15f5144
[RISCV] Remove duplicate vector conversion pseudos.
topperc Oct 30, 2024
744bbe0
Merge remote-tracking branch 'origin/main' into pr/redundant-pseudos
topperc Oct 30, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2623,6 +2623,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}

if (int Idx = RISCVII::getFRMOpNum(Desc);
Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN &&
!MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) {
ErrInfo = "dynamic rounding mode should read FRM";
return false;
}

return true;
}

Expand Down
131 changes: 8 additions & 123 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1130,46 +1130,6 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
let usesCustomInserter = 1;
}

class VPseudoUnaryNoMask_FRM<VReg RetClass,
VReg OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
}

class VPseudoUnaryMask_FRM<VReg RetClass,
VReg OpClass,
string Constraint = "",
bits<2> TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
let HasRoundModeOp = 1;
}

class VPseudoUnaryNoMaskGPROut :
Pseudo<(outs GPR:$rd),
(ins VR:$rs2, AVL:$vl, sew:$sew), []>,
Expand Down Expand Up @@ -3574,23 +3534,6 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
}
}


multiclass VPseudoConversionRM<VReg RetClass,
VReg Op1Class,
LMULInfo MInfo,
string Constraint = "",
int sew = 0,
bits<2> TargetConstraintType = 1> {
let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=2>;
}
}

multiclass VPseudoConversionNoExcept<VReg RetClass,
VReg Op1Class,
LMULInfo MInfo,
Expand All @@ -3616,14 +3559,6 @@ multiclass VPseudoVCVTI_V_RM {
}
}

multiclass VPseudoVCVTI_RM_V {
foreach m = MxListF in {
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
forcePassthruRead=true>;
}
}

multiclass VPseudoVFROUND_NOEXCEPT_V {
foreach m = MxListF in {
defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,
Expand All @@ -3641,15 +3576,6 @@ multiclass VPseudoVCVTF_V_RM {
}
}

multiclass VPseudoVCVTF_RM_V {
foreach m = MxListF in {
foreach e = SchedSEWSet<m.MX, isF=1>.val in
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, sew=e>,
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
forcePassthruRead=true>;
}
}

multiclass VPseudoVWCVTI_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
Expand All @@ -3668,15 +3594,6 @@ multiclass VPseudoVWCVTI_V_RM {
}
}

multiclass VPseudoVWCVTI_RM_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
forcePassthruRead=true>;
}
}

multiclass VPseudoVWCVTF_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in {
Expand Down Expand Up @@ -3717,15 +3634,6 @@ multiclass VPseudoVNCVTI_W_RM {
}
}

multiclass VPseudoVNCVTI_RM_W {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in {
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
forcePassthruRead=true>;
}
}

multiclass VPseudoVNCVTF_W_RM {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
Expand All @@ -3738,17 +3646,6 @@ multiclass VPseudoVNCVTF_W_RM {
}
}

multiclass VPseudoVNCVTF_RM_W {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e,
TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
forcePassthruRead=true>;
}
}

multiclass VPseudoVNCVTD_W {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
Expand Down Expand Up @@ -6479,7 +6376,7 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
}

Expand Down Expand Up @@ -6512,7 +6409,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
defm PseudoVFSQRT : VPseudoVSQR_V_RM;

//===----------------------------------------------------------------------===//
Expand All @@ -6524,7 +6421,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
defm PseudoVFREC7 : VPseudoVRCP_V_RM;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -6579,9 +6476,6 @@ defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;
defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;
}

defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V;
defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V;

defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;

Expand All @@ -6590,8 +6484,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;
defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;
}
defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V;
defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V;
} // mayRaiseFPException = true

//===----------------------------------------------------------------------===//
Expand All @@ -6602,8 +6494,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;
}
defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V;
defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V;

defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
Expand All @@ -6623,8 +6513,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;
}
defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W;
defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W;

defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
Expand All @@ -6633,12 +6521,11 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
}
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;

let hasSideEffects = 0, hasPostISelHook = 1 in
let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
}

defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
} // mayRaiseFPException = true
Expand Down Expand Up @@ -6674,8 +6561,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true,
hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
Expand All @@ -6687,9 +6573,8 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let IsRVVWideningReduction = 1,
hasSideEffects = 0,
mayRaiseFPException = true in {
let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true,
hasPostISelHook = 1 in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
}
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Expand Up @@ -2639,23 +2639,23 @@ foreach fvti = AllFloatVectors in {
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">;
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;
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Does this change imply that we could merge riscv_vfcvt_rm_xu_f_vl and riscv_vfcvt_xu_f_vl can be merged?

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#114306

defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;

defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">;
defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">;

defm : VPatConvertI2FPVL_V_RM<any_riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
defm : VPatConvertI2FPVL_V_RM<any_riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;

defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_RM_F_XU_V">;
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_RM_F_X_V">;
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;

// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_RM_XU_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_RM_X_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;

defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
Expand Down Expand Up @@ -2696,17 +2696,17 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_RM_XU_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_RM_X_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;

defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;

defm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;

defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_RM_F_XU_W">;
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">;
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_F_XU_W">;
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;

foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
Expand Down
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