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[mlir] Add description to amdgpu.dpp and rocdl.update.dpp #116598
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Thank you for submitting a Pull Request (PR) to the LLVM Project! This PR will be automatically labeled and the relevant teams will be notified. If you wish to, you can add reviewers by using the "Reviewers" section on this page. If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers. If you have further questions, they may be answered by the LLVM GitHub User Guide. You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums. |
@antiagainst Not sure a doc update is too trivial to be merged in MLIR. If so, it can be coalesced with other PR, e.g. gpu::shuffle lowering using dpp. |
@llvm/pr-subscribers-mlir-gpu @llvm/pr-subscribers-backend-amdgpu Author: Kyle Wang (knwng) ChangesAdd description to amdgpu.dpp and rocdl.update.dpp to explain their behaviors. Full diff: https://github.com/llvm/llvm-project/pull/116598.diff 2 Files Affected:
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
index 69745addfd748e..cb25655cc29eb8 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
@@ -437,6 +437,11 @@ def AMDGPU_DPPOp : AMDGPU_Op<"dpp", [SameTypeOperands, AllTypesMatch<["result",
let summary = "AMDGPU DPP operation";
let description = [{
This operation represents DPP functionality in a GPU program.
+
+ The behavior should be equivalent to:
+ v_mov_b32 `result` `old`
+ v_mov_b32 `result` `src` `kind` `row_mask` `bank_mask` `bound_ctrl`
+
DPP provides the following operations:
- Full crossbar in a group of four (`quad_perm`)
- Wavefront shift left by one lane (`wave_shl`)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 3695708439d91f..a2a86a3a8a2cf0 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -621,6 +621,15 @@ def ROCDL_DPPUpdateOp : ROCDL_IntrOp<"update.dpp", [], [0],
Arguments<(ins LLVM_Type:$old, LLVM_Type:$src, I32Attr:$dppCtrl, I32Attr:$rowMask,
I32Attr:$bankMask, I1Attr:$boundCtrl)> {
let results = (outs LLVM_Type:$res);
+ let summary = "Represent the DPP(Data-Parallel Primitives) functionality";
+ let description = [{
+ Represent the DPP(Data-Parallel Primitives) functionality,
+ which supports cross-lane data operations.
+
+ The behavior should be equivalent to:
+ v_mov_b32 `res` `old`
+ v_mov_b32 `res` `src` `dppCtrl` `rowMask` `bankMask` `boundCtrl`
+ }];
let assemblyFormat = [{
attr-dict $old `,` $src `with` $dppCtrl `,` $rowMask `,` $bankMask `,` $boundCtrl `:` type($src)
}];
|
@llvm/pr-subscribers-mlir Author: Kyle Wang (knwng) ChangesAdd description to amdgpu.dpp and rocdl.update.dpp to explain their behaviors. Full diff: https://github.com/llvm/llvm-project/pull/116598.diff 2 Files Affected:
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
index 69745addfd748e..cb25655cc29eb8 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
@@ -437,6 +437,11 @@ def AMDGPU_DPPOp : AMDGPU_Op<"dpp", [SameTypeOperands, AllTypesMatch<["result",
let summary = "AMDGPU DPP operation";
let description = [{
This operation represents DPP functionality in a GPU program.
+
+ The behavior should be equivalent to:
+ v_mov_b32 `result` `old`
+ v_mov_b32 `result` `src` `kind` `row_mask` `bank_mask` `bound_ctrl`
+
DPP provides the following operations:
- Full crossbar in a group of four (`quad_perm`)
- Wavefront shift left by one lane (`wave_shl`)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 3695708439d91f..a2a86a3a8a2cf0 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -621,6 +621,15 @@ def ROCDL_DPPUpdateOp : ROCDL_IntrOp<"update.dpp", [], [0],
Arguments<(ins LLVM_Type:$old, LLVM_Type:$src, I32Attr:$dppCtrl, I32Attr:$rowMask,
I32Attr:$bankMask, I1Attr:$boundCtrl)> {
let results = (outs LLVM_Type:$res);
+ let summary = "Represent the DPP(Data-Parallel Primitives) functionality";
+ let description = [{
+ Represent the DPP(Data-Parallel Primitives) functionality,
+ which supports cross-lane data operations.
+
+ The behavior should be equivalent to:
+ v_mov_b32 `res` `old`
+ v_mov_b32 `res` `src` `dppCtrl` `rowMask` `bankMask` `boundCtrl`
+ }];
let assemblyFormat = [{
attr-dict $old `,` $src `with` $dppCtrl `,` $rowMask `,` $bankMask `,` $boundCtrl `:` type($src)
}];
|
Add description to amdgpu.dpp and rocdl.update.dpp to explain their behaviors.