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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (7/11) #116833

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Jan 27, 2025
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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (7/11) #116833

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bf851bd
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (7/11)
momchil-velikov Nov 19, 2024
4a39cff
[fixup] Rebase, update tests, add tests for the new all-true patterns…
momchil-velikov Dec 20, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4280,7 +4280,7 @@ let Predicates = [HasSVE2p2orSME2p2] in {
defm SCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b0, "scvtf">;
defm UCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b1, "ucvtf">;
// Signed integer base 2 logarithm of fp value, zeroing predicate
defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;
defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb", int_aarch64_sve_flogb>;

// SVE2 integer unary operations, zeroing predicate
def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;
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6 changes: 5 additions & 1 deletion llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -3316,10 +3316,14 @@ multiclass sve_fp_z2op_p_zd_c<bit U, string asm> {
def _DtoD : sve_fp_z2op_p_zd<{ 0b111011, U }, asm, ZPR64, ZPR64>;
}

multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
multiclass sve_fp_z2op_p_zd_d_flogb<string asm, SDPatternOperator op> {
def _H : sve_fp_z2op_p_zd<0b0011001, asm, ZPR16, ZPR16>;
def _S : sve_fp_z2op_p_zd<0b0011010, asm, ZPR32, ZPR32>;
def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;

defm : SVE_3_Op_UndefZero_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
defm : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
defm : SVE_3_Op_UndefZero_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_fp_z2op_p_zd_b_0<string asm, string op> {
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258 changes: 258 additions & 0 deletions llvm/test/CodeGen/AArch64/zeroing-forms-flogb.ll
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@@ -0,0 +1,258 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2

; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2

target triple = "aarch64-linux"

define <vscale x 8 x i16> @test_svlogb_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svlogb_f16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.h, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x i16> %0
}

define <vscale x 8 x i16> @test_svlogb_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svlogb_f16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x i16> %0
}

define <vscale x 8 x i16> @test_svlogb_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svlogb_f16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #0 // =0x0
; CHECK-NEXT: flogb z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x i16> %0
}

define <vscale x 4 x i32> @test_svlogb_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svlogb_f32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.s, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x i32> %0
}

define <vscale x 4 x i32> @test_svlogb_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svlogb_f32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x i32> %0
}

define <vscale x 4 x i32> @test_svlogb_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svlogb_f32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: flogb z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x i32> %0
}

define <vscale x 2 x i64> @test_svlogb_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svlogb_f64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.d, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x i64> %0
}

define <vscale x 2 x i64> @test_svlogb_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svlogb_f64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: flogb z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x i64> %0
}

define <vscale x 2 x i64> @test_svlogb_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svlogb_f64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: flogb z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_f64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x i64> %0
}

define <vscale x 8 x i16> @test_svlogb_nxv8f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svlogb_nxv8f16_ptrue_u:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: flogb z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv8f16_ptrue_u:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.h
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x i16> %0
}

define <vscale x 8 x i16> @test_svlogb_nxv8f16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x half> %y) {
; CHECK-LABEL: test_svlogb_nxv8f16_ptrue:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: flogb z0.h, p0/m, z2.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv8f16_ptrue:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.h
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z2.h
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x half> %y)
ret <vscale x 8 x i16> %0
}

define <vscale x 4 x i32> @test_svlogb_nxv4f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svlogb_nxv4f32_ptrue_u:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: flogb z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv4f32_ptrue_u:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.s
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x i32> %0
}

define <vscale x 4 x i32> @test_svlogb_nxv4f32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x float> %y) {
; CHECK-LABEL: test_svlogb_nxv4f32_ptrue:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: flogb z0.s, p0/m, z2.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv4f32_ptrue:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.s
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z2.s
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x float> %y)
ret <vscale x 4 x i32> %0
}

define <vscale x 2 x i64> @test_svlogb_nxv2f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svlogb_nxv2f64_ptrue_u:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: flogb z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv2f64_ptrue_u:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.d
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x i64> %0
}

define <vscale x 2 x i64> @test_svlogb_nxv2f64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x double> %y) {
; CHECK-LABEL: test_svlogb_nxv2f64_ptrue:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: flogb z0.d, p0/m, z2.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svlogb_nxv2f64_ptrue:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: ptrue p0.d
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z2.d
; CHECK-2p2-NEXT: ret
entry:
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
ret <vscale x 2 x i64> %0
}

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