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[Clang][Xtensa] Add Xtensa target. #118008
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//===--- Xtensa.cpp - Implement Xtensa target feature support -------------===// | ||
// | ||
// The LLVM Compiler Infrastructure | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file implements Xtensa TargetInfo objects. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#include "Xtensa.h" | ||
#include "clang/Basic/Builtins.h" | ||
#include "clang/Basic/MacroBuilder.h" | ||
#include "clang/Basic/TargetBuiltins.h" | ||
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using namespace clang; | ||
using namespace clang::targets; | ||
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void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, | ||
MacroBuilder &Builder) const { | ||
Builder.defineMacro("__xtensa__"); | ||
Builder.defineMacro("__XTENSA__"); | ||
if (BigEndian) | ||
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Builder.defineMacro("__XTENSA_EB__"); | ||
else | ||
Builder.defineMacro("__XTENSA_EL__"); | ||
Builder.defineMacro("__XCHAL_HAVE_BE", BigEndian ? "1" : "0"); | ||
Builder.defineMacro("__XCHAL_HAVE_ABS"); // core arch | ||
Builder.defineMacro("__XCHAL_HAVE_ADDX"); // core arch | ||
Builder.defineMacro("__XCHAL_HAVE_L32R"); // core arch | ||
} |
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//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===// | ||
// | ||
// The LLVM Compiler Infrastructure | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file declares Xtensa TargetInfo objects. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H | ||
#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H | ||
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#include "clang/Basic/TargetInfo.h" | ||
#include "clang/Basic/TargetOptions.h" | ||
#include "llvm/ADT/StringSwitch.h" | ||
#include "llvm/Support/Compiler.h" | ||
#include "llvm/TargetParser/Triple.h" | ||
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#include "clang/Basic/Builtins.h" | ||
#include "clang/Basic/MacroBuilder.h" | ||
#include "clang/Basic/TargetBuiltins.h" | ||
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namespace clang { | ||
namespace targets { | ||
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class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { | ||
static const Builtin::Info BuiltinInfo[]; | ||
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protected: | ||
std::string CPU; | ||
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public: | ||
XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) | ||
: TargetInfo(Triple) { | ||
// no big-endianess support yet | ||
BigEndian = false; | ||
NoAsmVariants = true; | ||
LongLongAlign = 64; | ||
SuitableAlign = 32; | ||
DoubleAlign = LongDoubleAlign = 64; | ||
SizeType = UnsignedInt; | ||
PtrDiffType = SignedInt; | ||
IntPtrType = SignedInt; | ||
WCharType = SignedInt; | ||
WIntType = UnsignedInt; | ||
UseZeroLengthBitfieldAlignment = true; | ||
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; | ||
resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"); | ||
} | ||
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void getTargetDefines(const LangOptions &Opts, | ||
MacroBuilder &Builder) const override; | ||
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ArrayRef<Builtin::Info> getTargetBuiltins() const override { | ||
return std::nullopt; | ||
} | ||
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BuiltinVaListKind getBuiltinVaListKind() const override { | ||
return TargetInfo::XtensaABIBuiltinVaList; | ||
} | ||
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std::string_view getClobbers() const override { return ""; } | ||
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ArrayRef<const char *> getGCCRegNames() const override { | ||
static const char *const GCCRegNames[] = { | ||
// General register name | ||
"a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", | ||
"a11", "a12", "a13", "a14", "a15", | ||
// Special register name | ||
"sar"}; | ||
return llvm::ArrayRef(GCCRegNames); | ||
} | ||
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { | ||
return std::nullopt; | ||
} | ||
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bool validateAsmConstraint(const char *&Name, | ||
TargetInfo::ConstraintInfo &Info) const override { | ||
switch (*Name) { | ||
default: | ||
return false; | ||
case 'a': | ||
Info.setAllowsRegister(); | ||
return true; | ||
} | ||
return false; | ||
} | ||
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int getEHDataRegisterNumber(unsigned RegNo) const override { | ||
return (RegNo < 2) ? RegNo : -1; | ||
} | ||
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bool isValidCPUName(StringRef Name) const override { | ||
return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false); | ||
} | ||
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bool setCPU(const std::string &Name) override { | ||
CPU = Name; | ||
return isValidCPUName(Name); | ||
} | ||
}; | ||
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} // namespace targets | ||
} // namespace clang | ||
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H |
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