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[AArch64] Add intrinsics for SME FP8 FDOT LANE instructions #118492
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609cf3f
[AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray 605ccdf
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray 863a803
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray 4dba844
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray e2e9fd7
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray fb5ec1c
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray 605157d
Update llvm/include/llvm/IR/IntrinsicsAArch64.td
jthackray 16684b1
fixup! [AArch64] Add intrinsics for SME FP8 FDOT LANE instructions
jthackray b477bd7
Merge branch 'main' into main
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96 changes: 96 additions & 0 deletions
96
clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,96 @@ | ||
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 | ||
| // REQUIRES: aarch64-registered-target | ||
| #include <arm_sme.h> | ||
|
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| // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
| // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
| #include <arm_sme.h> | ||
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| #ifdef SVE_OVERLOADED_FORMS | ||
| #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 | ||
| #else | ||
| #define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 | ||
| #endif | ||
|
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| // CHECK-LABEL: define dso_local void @test_svdot_lane_za32_f8_vg1x2( | ||
| // CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CHECK-NEXT: ret void | ||
| // | ||
| // CPP-CHECK-LABEL: define dso_local void @_Z29test_svdot_lane_za32_f8_vg1x2j13svmfloat8x2_tu13__SVMfloat8_tm( | ||
| // CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CPP-CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CPP-CHECK-NEXT: ret void | ||
| // | ||
| void test_svdot_lane_za32_f8_vg1x2(uint32_t slice, svmfloat8x2_t zn, | ||
| svmfloat8_t zm, fpm_t fpmr) | ||
| __arm_streaming __arm_inout("za") { | ||
| SVE_ACLE_FUNC(svdot_lane_za32,_mf8,_vg1x2_fpm)(slice, zn, zm, 3, fpmr); | ||
| } | ||
|
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| // CHECK-LABEL: define dso_local void @test_svdot_lane_za32_f8_vg1x4( | ||
| // CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CHECK-NEXT: ret void | ||
| // | ||
| // CPP-CHECK-LABEL: define dso_local void @_Z29test_svdot_lane_za32_f8_vg1x4j13svmfloat8x4_tu13__SVMfloat8_tm( | ||
| // CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CPP-CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CPP-CHECK-NEXT: ret void | ||
| // | ||
| void test_svdot_lane_za32_f8_vg1x4(uint32_t slice, svmfloat8x4_t zn, | ||
| svmfloat8_t zm, fpm_t fpmr) | ||
| __arm_streaming __arm_inout("za") { | ||
| SVE_ACLE_FUNC(svdot_lane_za32,_mf8,_vg1x4_fpm)(slice, zn, zm, 3, fpmr); | ||
| } | ||
|
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||
| // CHECK-LABEL: define dso_local void @test_svdot_lane_za16_f8_vg1x2( | ||
| // CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CHECK-NEXT: ret void | ||
| // | ||
| // CPP-CHECK-LABEL: define dso_local void @_Z29test_svdot_lane_za16_f8_vg1x2j13svmfloat8x2_tu13__SVMfloat8_tm( | ||
| // CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CPP-CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CPP-CHECK-NEXT: ret void | ||
| // | ||
| void test_svdot_lane_za16_f8_vg1x2(uint32_t slice, svmfloat8x2_t zn, | ||
| svmfloat8_t zm, fpm_t fpmr) | ||
| __arm_streaming __arm_inout("za") { | ||
| SVE_ACLE_FUNC(svdot_lane_za16,_mf8,_vg1x2_fpm)(slice, zn, zm, 3, fpmr); | ||
| } | ||
|
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||
| // CHECK-LABEL: define dso_local void @test_svdot_lane_za16_f8_vg1x4( | ||
| // CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CHECK-NEXT: ret void | ||
| // | ||
| // CPP-CHECK-LABEL: define dso_local void @_Z29test_svdot_lane_za16_f8_vg1x4j13svmfloat8x4_tu13__SVMfloat8_tm( | ||
| // CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZN_COERCE2:%.*]], <vscale x 16 x i8> [[ZN_COERCE3:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] { | ||
| // CPP-CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]]) | ||
| // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZN_COERCE2]], <vscale x 16 x i8> [[ZN_COERCE3]], <vscale x 16 x i8> [[ZM]], i32 3) | ||
| // CPP-CHECK-NEXT: ret void | ||
| // | ||
| void test_svdot_lane_za16_f8_vg1x4(uint32_t slice, svmfloat8x4_t zn, | ||
| svmfloat8_t zm, fpm_t fpmr) | ||
| __arm_streaming __arm_inout("za") { | ||
| SVE_ACLE_FUNC(svdot_lane_za16,_mf8,_vg1x4_fpm)(slice, zn, zm, 3, fpmr); | ||
| } |
38 changes: 38 additions & 0 deletions
38
clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fdot.c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -verify -emit-llvm -o - %s | ||
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| // REQUIRES: aarch64-registered-target | ||
|
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| #include <arm_sme.h> | ||
|
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| void test_features(uint32_t slice, svmfloat8_t f8, svmfloat8x2_t f8x2, | ||
| svmfloat8x4_t f8x4, uint64_t fpmr) __arm_streaming __arm_inout("za") { | ||
| // expected-error@+1 {{'svdot_lane_za32_mf8_vg1x2_fpm' needs target feature sme,sme-f8f32}} | ||
| svdot_lane_za32_mf8_vg1x2_fpm(slice, f8x2, f8, 3, fpmr); | ||
| // expected-error@+1 {{'svdot_lane_za32_mf8_vg1x4_fpm' needs target feature sme,sme-f8f32}} | ||
| svdot_lane_za32_mf8_vg1x4_fpm(slice, f8x4, f8, 3, fpmr); | ||
| // expected-error@+1 {{'svdot_lane_za16_mf8_vg1x2_fpm' needs target feature sme,sme-f8f16}} | ||
| svdot_lane_za16_mf8_vg1x2_fpm(slice, f8x2, f8, 3, fpmr); | ||
| // expected-error@+1 {{'svdot_lane_za16_mf8_vg1x4_fpm' needs target feature sme,sme-f8f16}} | ||
| svdot_lane_za16_mf8_vg1x4_fpm(slice, f8x4, f8, 3, fpmr); | ||
| } | ||
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| void test_imm(uint32_t slice, svmfloat8_t f8, svmfloat8x2_t f8x2, | ||
| svmfloat8x4_t f8x4, uint64_t fpmr) __arm_streaming __arm_inout("za") { | ||
| // expected-error@+1{{argument value 18446744073709551615 is outside the valid range [0, 3]}} | ||
| svdot_lane_za32_mf8_vg1x2_fpm(slice, f8x2, f8, -1, fpmr); | ||
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| // expected-error@+1{{argument value 18446744073709551615 is outside the valid range [0, 3]}} | ||
| svdot_lane_za32_mf8_vg1x4_fpm(slice, f8x4, f8, -1, fpmr); | ||
| // expected-error@+1{{argument value 18446744073709551615 is outside the valid range [0, 7]}} | ||
| svdot_lane_za16_mf8_vg1x2_fpm(slice, f8x2, f8, -1, fpmr); | ||
| // expected-error@+1{{argument value 18446744073709551615 is outside the valid range [0, 7]}} | ||
| svdot_lane_za16_mf8_vg1x4_fpm(slice, f8x4, f8, -1, fpmr); | ||
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| // expected-error@+1{{argument value 4 is outside the valid range [0, 3]}} | ||
| svdot_lane_za32_mf8_vg1x2_fpm(slice, f8x2, f8, 4, fpmr); | ||
| // expected-error@+1{{argument value 4 is outside the valid range [0, 3]}} | ||
| svdot_lane_za32_mf8_vg1x4_fpm(slice, f8x4, f8, 4, fpmr); | ||
| // expected-error@+1{{argument value 8 is outside the valid range [0, 7]}} | ||
| svdot_lane_za16_mf8_vg1x2_fpm(slice, f8x2, f8, 8, fpmr); | ||
| // expected-error@+1{{argument value 8 is outside the valid range [0, 7]}} | ||
| svdot_lane_za16_mf8_vg1x4_fpm(slice, f8x4, f8, 8, fpmr); | ||
| } | ||
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