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[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal #118509

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Merged
merged 4 commits into from
Dec 4, 2024
Merged

[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal #118509

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743d25b
[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal
preames Dec 2, 2024
a75537d
clang-format
preames Dec 3, 2024
7ee38b8
Merge branch 'main' into pr-riscv-deinterleave48-shuffle-lowering
preames Dec 3, 2024
26ab344
Adddress review comment
preames Dec 3, 2024
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9 changes: 1 addition & 8 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5314,15 +5314,8 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
unsigned Index = 0;
if (ShuffleVectorInst::isDeInterleaveMaskOfFactor(Mask, Factor, Index) &&
1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2)) {
if (Src.getValueType() == VT) {
EVT WideVT = VT.getDoubleNumVectorElementsVT();
Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
DAG.getUNDEF(WideVT), Src,
DAG.getVectorIdxConstant(0, DL));
}
if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2))
return getDeinterleaveShiftAndTrunc(DL, VT, Src, Factor, Index, DAG);
}
}
}
}
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19 changes: 10 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
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Expand Up @@ -24,19 +24,20 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
; CHECK-NEXT: vadd.vi v12, v11, -16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v8, 2
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v11, v11, -15
; CHECK-NEXT: vmerge.vim v13, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
; CHECK-NEXT: vnsrl.wi v8, v14, 0
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vrgather.vv v8, v13, v12, v0.t
; CHECK-NEXT: vnsrl.wi v12, v14, 8
; CHECK-NEXT: vmsne.vi v10, v8, 0
; CHECK-NEXT: vrgather.vv v12, v13, v11, v0.t
; CHECK-NEXT: vmsne.vi v8, v12, 0
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vv v10, v13, v12, v0.t
; CHECK-NEXT: vrgather.vv v8, v13, v11, v0.t
; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: ret
%vec = load <32 x i1>, ptr %p
%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
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5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
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Expand Up @@ -104,7 +104,7 @@ define <4 x i32> @v4i32_v16i32(<16 x i32>) {
; RV32-NEXT: vmv.v.i v0, 10
; RV32-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV32-NEXT: vslideup.vi v14, v12, 1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vnsrl.wx v12, v8, a0
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV32-NEXT: vslidedown.vi v8, v8, 8
Expand All @@ -116,9 +116,8 @@ define <4 x i32> @v4i32_v16i32(<16 x i32>) {
; RV64-LABEL: v4i32_v16i32:
; RV64: # %bb.0:
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v0, 10
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vnsrl.wx v12, v8, a0
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 8
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52 changes: 38 additions & 14 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
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Expand Up @@ -441,13 +441,25 @@ entry:
}

define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_single_src:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
; V-LABEL: vnsrl_0_i8_single_src:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; V-NEXT: vle8.v v8, (a0)
; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
; V-NEXT: vnsrl.wi v8, v8, 0
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; V-NEXT: vse8.v v8, (a1)
; V-NEXT: ret
;
; ZVE32F-LABEL: vnsrl_0_i8_single_src:
; ZVE32F: # %bb.0: # %entry
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZVE32F-NEXT: vse8.v v8, (a1)
; ZVE32F-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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Is the test and the one below effectively the same? Indices 8, 10, 12, 14 all point to a poison input so they should be converted to a -1 in the mask before shuffle lowering I think.

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I agree. I reworked these slightly in f947d5a to improve the coverage.

Expand All @@ -456,13 +468,25 @@ entry:
}

define void @vnsrl_0_i8_single_src2(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_single_src2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
; V-LABEL: vnsrl_0_i8_single_src2:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; V-NEXT: vle8.v v8, (a0)
; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
; V-NEXT: vnsrl.wi v8, v8, 0
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; V-NEXT: vse8.v v8, (a1)
; V-NEXT: ret
;
; ZVE32F-LABEL: vnsrl_0_i8_single_src2:
; ZVE32F: # %bb.0: # %entry
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZVE32F-NEXT: vse8.v v8, (a1)
; ZVE32F-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
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17 changes: 9 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
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Expand Up @@ -19,18 +19,19 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
; CHECK-NEXT: vadd.vi v8, v12, -16
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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This whole sequence is more complicated than it probably needs to be. Looks like the promotion to an i8 vector interferes with the matching of a deinterleave with 2 extract_subvector inputs because the zero_extend is between the extracts and the shuffle.

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Yeah, room for improvement, definitely. Not currently that interested in codegen, but if we decide to focus on that at some point, it's not the only one which has room for improvement.

; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vadd.vi v10, v12, -16
; CHECK-NEXT: vadd.vi v12, v12, -15
; CHECK-NEXT: vnsrl.wi v10, v14, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v13, v8, 0
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vrgather.vv v10, v11, v8, v0.t
; CHECK-NEXT: vnsrl.wi v8, v14, 8
; CHECK-NEXT: vmsne.vi v10, v10, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vv v13, v11, v10, v0.t
; CHECK-NEXT: vrgather.vv v8, v11, v12, v0.t
; CHECK-NEXT: vmsne.vi v0, v13, 0
; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
ret {<16 x i1>, <16 x i1>} %retval
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