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[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal #118509

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Dec 4, 2024
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[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal #118509

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[RISCV] Match deinterleave(4,8) shuffles to SHL/TRUNC when legal
preames Dec 2, 2024
a75537d
clang-format
preames Dec 3, 2024
7ee38b8
Merge branch 'main' into pr-riscv-deinterleave48-shuffle-lowering
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119 changes: 54 additions & 65 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4442,38 +4442,13 @@ static SDValue lowerScalarInsert(SDValue Scalar, SDValue VL, MVT VT,
unsigned ExtOpc =
isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT,
DAG.getUNDEF(VT), Scalar, VL);
}

// Is this a shuffle extracts either the even or odd elements of a vector?
// That is, specifically, either (a) or (b) in the options below.
// Single operand shuffle is easy:
// a) t35: v8i8 = vector_shuffle<0,2,4,6,u,u,u,u> t34, undef
// b) t35: v8i8 = vector_shuffle<1,3,5,7,u,u,u,u> t34, undef
// Double operand shuffle:
// t34: v8i8 = extract_subvector t11, Constant:i64<0>
// t33: v8i8 = extract_subvector t11, Constant:i64<8>
// a) t35: v8i8 = vector_shuffle<0,2,4,6,8,10,12,14> t34, t33
// b) t35: v8i8 = vector_shuffle<1,3,5,7,9,11,13,15> t34, t33
static SDValue isDeinterleaveShuffle(MVT VT, MVT ContainerVT, SDValue V1,
SDValue V2, ArrayRef<int> Mask,
const RISCVSubtarget &Subtarget) {
// Need to be able to widen the vector.
if (VT.getScalarSizeInBits() >= Subtarget.getELen())
return SDValue();

// First index must be the first even or odd element from V1.
if (Mask[0] != 0 && Mask[0] != 1)
return SDValue();

// The others must increase by 2 each time.
for (unsigned i = 1; i != Mask.size(); ++i)
if (Mask[i] != -1 && Mask[i] != Mask[0] + (int)i * 2)
return SDValue();
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT), Scalar,
VL);
}

if (1 == count_if(Mask, [](int Idx) { return Idx != -1; }))
return SDValue();
// Can this shuffle be performed on exactly one (possibly larger) input?
static SDValue getSingleShuffleSrc(MVT VT, MVT ContainerVT, SDValue V1,
SDValue V2) {

if (V2.isUndef() &&
RISCVTargetLowering::getLMUL(ContainerVT) != RISCVII::VLMUL::LMUL_8)
Expand All @@ -4490,12 +4465,13 @@ static SDValue isDeinterleaveShuffle(MVT VT, MVT ContainerVT, SDValue V1,
return SDValue();

// Src needs to have twice the number of elements.
if (Src.getValueType().getVectorNumElements() != (Mask.size() * 2))
unsigned NumElts = VT.getVectorNumElements();
if (Src.getValueType().getVectorNumElements() != (NumElts * 2))
return SDValue();

// The extracts must extract the two halves of the source.
if (V1.getConstantOperandVal(1) != 0 ||
V2.getConstantOperandVal(1) != Mask.size())
V2.getConstantOperandVal(1) != NumElts)
return SDValue();

return Src;
Expand Down Expand Up @@ -4612,36 +4588,29 @@ static int isElementRotate(int &LoSrc, int &HiSrc, ArrayRef<int> Mask) {
return Rotation;
}

// Lower a deinterleave shuffle to vnsrl.
// [a, p, b, q, c, r, d, s] -> [a, b, c, d] (EvenElts == true)
// -> [p, q, r, s] (EvenElts == false)
// VT is the type of the vector to return, <[vscale x ]n x ty>
// Src is the vector to deinterleave of type <[vscale x ]n*2 x ty>
static SDValue getDeinterleaveViaVNSRL(const SDLoc &DL, MVT VT, SDValue Src,
bool EvenElts, SelectionDAG &DAG) {
// The result is a vector of type <m x n x ty>. The source is a vector of
// type <m x n*2 x ty> (For the single source case, the high half is undef)
if (Src.getValueType() == VT) {
EVT WideVT = VT.getDoubleNumVectorElementsVT();
Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, DAG.getUNDEF(WideVT),
Src, DAG.getVectorIdxConstant(0, DL));
}

// Bitcast the source vector from <m x n*2 x ty> -> <m x n x ty*2>
// This also converts FP to int.
// Lower a deinterleave shuffle to SRL and TRUNC. Factor must be
// 2, 4, 8 and the integer type Factor-times larger than VT's
// element type must be a legal element type.
// [a, p, b, q, c, r, d, s] -> [a, b, c, d] (Factor=2, Index=0)
// -> [p, q, r, s] (Factor=2, Index=1)
static SDValue getDeinterleaveShiftAndTrunc(const SDLoc &DL, MVT VT,
SDValue Src, unsigned Factor,
unsigned Index, SelectionDAG &DAG) {
unsigned EltBits = VT.getScalarSizeInBits();
MVT WideSrcVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * 2),
VT.getVectorElementCount());
ElementCount SrcEC = Src.getValueType().getVectorElementCount();
MVT WideSrcVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Factor),
SrcEC.divideCoefficientBy(Factor));
MVT ResVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits),
SrcEC.divideCoefficientBy(Factor));
Src = DAG.getBitcast(WideSrcVT, Src);

MVT IntVT = VT.changeVectorElementTypeToInteger();

// If we want even elements, then the shift amount is 0. Otherwise, shift by
// the original element size.
unsigned Shift = EvenElts ? 0 : EltBits;
unsigned Shift = Index * EltBits;
SDValue Res = DAG.getNode(ISD::SRL, DL, WideSrcVT, Src,
DAG.getConstant(Shift, DL, WideSrcVT));
Res = DAG.getNode(ISD::TRUNCATE, DL, IntVT, Res);
Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT, Res);
MVT IntVT = VT.changeVectorElementTypeToInteger();
Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, IntVT, DAG.getUNDEF(IntVT), Res,
DAG.getVectorIdxConstant(0, DL));
return DAG.getBitcast(VT, Res);
}

Expand Down Expand Up @@ -5332,11 +5301,31 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
if (ShuffleVectorInst::isReverseMask(Mask, NumElts) && V2.isUndef())
return DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1);

// If this is a deinterleave and we can widen the vector, then we can use
// vnsrl to deinterleave.
if (SDValue Src =
isDeinterleaveShuffle(VT, ContainerVT, V1, V2, Mask, Subtarget))
return getDeinterleaveViaVNSRL(DL, VT, Src, Mask[0] == 0, DAG);
// If this is a deinterleave(2,4,8) and we can widen the vector, then we can
// use shift and truncate to perform the shuffle.
// TODO: For Factor=6, we can perform the first step of the deinterleave via
// shift-and-trunc reducing total cost for everything except an mf8 result.
// TODO: For Factor=4,8, we can do the same when the ratio isn't high enough
// to do the entire operation.
if (VT.getScalarSizeInBits() < Subtarget.getELen()) {
const unsigned MaxFactor = Subtarget.getELen() / VT.getScalarSizeInBits();
assert(MaxFactor == 2 || MaxFactor == 4 || MaxFactor == 8);
for (unsigned Factor = 2; Factor <= MaxFactor; Factor <<= 1) {
unsigned Index = 0;
if (ShuffleVectorInst::isDeInterleaveMaskOfFactor(Mask, Factor, Index) &&
1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2)) {
if (Src.getValueType() == VT) {
EVT WideVT = VT.getDoubleNumVectorElementsVT();
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Not directly related to this patch, but I think for large minimum VLEN this might create an illegal type. There's an attempt to protect this in getSingleShuffleSrc by checking RISCVTargetLowering::getLMUL(ContainerVT) != RISCVII::VLMUL::LMUL_8. For sufficiently large minimum VLEN, LMUL==4 can be the largest legal type and LMUL=8 would be an illegal type because we don't have a large enough MVT to represent it.

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Oh, nasty. Do you have a recommended idiom for checking this case? Example code I can copy from?

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Do we need to widen here at all? We used to need to widen so that the narrow result type after dividing factor 2 was exactly VT. With larger factors we have to pad back up to VT at the end now. Does the padding at the end cover this case?

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Hm, let me play with that. I ran into a similar-ish case in a follow on change which impacted code quality, so let's see if reworking this slight does too.

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I made this change, it does work. It also introduces some additional VL and VTYPE toggles, which is why I think we didn't do this before.

Two questions for you.

  1. Are we bothered by the toggles? I can probably eliminate them < m1 by adding back the removed code, but conditional on LMUL. For the > m2 cases, this is probably an improvement. We could potentially treat this a generic improvement to add to e.g. VLOptimizer too.

  2. Do we want to separate this change into it's own review? It feels somewhat borderline to me honestly, so will defer to your preference.

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Are we bothered by the toggles? I can probably eliminate them < m1 by adding back the removed code, but conditional on LMUL. For the > m2 cases, this is probably an improvement. We could potentially treat this a generic improvement to add to e.g. VLOptimizer too.

I agree its probably an improvement for the wide LMUL. I don't think I'm bothered by the toggles. Some of the tests are producing undefined elements in the upper half of the shuffle result and then using them in a later instruction. Is that likely in real code?

Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
DAG.getUNDEF(WideVT), Src,
DAG.getVectorIdxConstant(0, DL));
}
return getDeinterleaveShiftAndTrunc(DL, VT, Src, Factor, Index, DAG);
}
}
}
}

if (SDValue V =
lowerVECTOR_SHUFFLEAsVSlideup(DL, VT, V1, V2, Mask, Subtarget, DAG))
Expand Down Expand Up @@ -10739,8 +10728,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
// We can deinterleave through vnsrl.wi if the element type is smaller than
// ELEN
if (VecVT.getScalarSizeInBits() < Subtarget.getELen()) {
SDValue Even = getDeinterleaveViaVNSRL(DL, VecVT, Concat, true, DAG);
SDValue Odd = getDeinterleaveViaVNSRL(DL, VecVT, Concat, false, DAG);
SDValue Even = getDeinterleaveShiftAndTrunc(DL, VecVT, Concat, 2, 0, DAG);
SDValue Odd = getDeinterleaveShiftAndTrunc(DL, VecVT, Concat, 2, 1, DAG);
return DAG.getMergeValues({Even, Odd}, DL);
}

Expand Down
22 changes: 5 additions & 17 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
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Expand Up @@ -721,24 +721,12 @@ define <8 x i32> @shuffle_v8i32_2(<8 x i32> %x, <8 x i32> %y) {
define <8 x i8> @shuffle_v64i8_v8i8(<64 x i8> %wide.vec) {
; CHECK-LABEL: shuffle_v64i8_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 4112
; CHECK-NEXT: li a1, 240
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: addi a0, a0, 257
; CHECK-NEXT: vmv.s.x v14, a0
; CHECK-NEXT: lui a0, 98561
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcompress.vm v12, v8, v14
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: addi a0, a0, -2048
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vrgather.vv v12, v8, v10, v0.t
; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%s = shufflevector <64 x i8> %wide.vec, <64 x i8> poison, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 48, i32 56>
ret <8 x i8> %s
Expand Down
61 changes: 23 additions & 38 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
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Expand Up @@ -67,22 +67,12 @@ define void @deinterleave4_0_i8(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 4
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vsll.vi v9, v9, 2
; CHECK-NEXT: vadd.vi v9, v9, -8
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
; CHECK-NEXT: vse8.v v10, (a1)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
Expand All @@ -96,20 +86,11 @@ define void @deinterleave4_8_i8(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v9, 4
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v11, v9, v10
; CHECK-NEXT: vwmaccu.vx v11, a0, v10
; CHECK-NEXT: li a0, 34
; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vcompress.vm v10, v8, v9
; CHECK-NEXT: vmerge.vvm v8, v10, v11, v0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -268,10 +249,12 @@ define void @deinterleave8_0_i8(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
Expand All @@ -287,12 +270,14 @@ define void @deinterleave8_8_i8(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, -3
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v9, v8, 1, v0.t
; CHECK-NEXT: vse8.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
Expand Down
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