[AMDGPU][True16][MC] test update for v_add/sub_f16 in true16 #118926
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-mc Author: Brox Chen (broxigarchen) ChangesThis is a NFC change. Update mc test for v_add/sub_f16 in true16 format. MC source change was done by previous patch and automatically enabled by t16 pesudo Patch is 180.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/118926.diff 23 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 128c7756191181..32b22041411032 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1818,10 +1818,8 @@ defm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x02f,
"V_CVT_PKRTZ_F16_F32", "v_cvt_pk_rtz_f16_f32">;
defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;
-defm V_ADD_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">;
-defm V_ADD_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">;
-defm V_SUB_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">;
-defm V_SUB_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">;
+defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;
+defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
index 7d850ec92aadb1..7a538ba7b4c54a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
@@ -124,50 +124,65 @@ v_add_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
// W64: v_add_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_add_f16 v5, v1, v2
-// GFX11: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x64]
+v_add_f16 v5.l, v1.l, v2.l
+// GFX11: v_add_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x64]
-v_add_f16 v5, v127, v2
-// GFX11: v_add_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x64]
+v_add_f16 v5.l, v127.l, v2.l
+// GFX11: v_add_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x64]
-v_add_f16 v5, s1, v2
-// GFX11: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x64]
+v_add_f16 v5.l, s1, v2.l
+// GFX11: v_add_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x64]
-v_add_f16 v5, s105, v2
-// GFX11: v_add_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x64]
+v_add_f16 v5.l, s105, v2.l
+// GFX11: v_add_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x64]
-v_add_f16 v5, vcc_lo, v2
-// GFX11: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x64]
+v_add_f16 v5.l, vcc_lo, v2.l
+// GFX11: v_add_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x64]
-v_add_f16 v5, vcc_hi, v2
-// GFX11: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x64]
+v_add_f16 v5.l, vcc_hi, v2.l
+// GFX11: v_add_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x64]
-v_add_f16 v5, ttmp15, v2
-// GFX11: v_add_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x64]
+v_add_f16 v5.l, ttmp15, v2.l
+// GFX11: v_add_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x64]
-v_add_f16 v5, m0, v2
-// GFX11: v_add_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x64]
+v_add_f16 v5.l, m0, v2.l
+// GFX11: v_add_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x64]
-v_add_f16 v5, exec_lo, v2
-// GFX11: v_add_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x64]
+v_add_f16 v5.l, exec_lo, v2.l
+// GFX11: v_add_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x64]
-v_add_f16 v5, exec_hi, v2
-// GFX11: v_add_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x64]
+v_add_f16 v5.l, exec_hi, v2.l
+// GFX11: v_add_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x64]
-v_add_f16 v5, null, v2
-// GFX11: v_add_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x64]
+v_add_f16 v5.l, null, v2.l
+// GFX11: v_add_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x64]
-v_add_f16 v5, -1, v2
-// GFX11: v_add_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x64]
+v_add_f16 v5.l, -1, v2.l
+// GFX11: v_add_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x64]
-v_add_f16 v5, 0.5, v2
-// GFX11: v_add_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x64]
+v_add_f16 v5.l, 0.5, v2.l
+// GFX11: v_add_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x64]
-v_add_f16 v5, src_scc, v2
-// GFX11: v_add_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x64]
+v_add_f16 v5.l, src_scc, v2.l
+// GFX11: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64]
-v_add_f16 v127, 0xfe0b, v127
-// GFX11: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
+v_add_f16 v127.l, 0xfe0b, v127.l
+// GFX11: v_add_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
+
+v_add_f16 v5.l, v1.h, v2.l
+// GFX11: v_add_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x64]
+
+v_add_f16 v5.l, v127.h, v2.l
+// GFX11: v_add_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x64]
+
+v_add_f16 v127.l, 0.5, v127.l
+// GFX11: v_add_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x64]
+
+v_add_f16 v5.h, src_scc, v2.h
+// GFX11: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65]
+
+v_add_f16 v127.h, 0xfe0b, v127.h
+// GFX11: v_add_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00]
v_add_f32 v5, v1, v2
// GFX11: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06]
@@ -2074,50 +2089,65 @@ v_sub_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
// W64: v_sub_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_sub_f16 v5, v1, v2
-// GFX11: v_sub_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x66]
+v_sub_f16 v5.l, v1.l, v2.l
+// GFX11: v_sub_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x66]
+
+v_sub_f16 v5.l, v127.l, v2.l
+// GFX11: v_sub_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x66]
+
+v_sub_f16 v5.l, s1, v2.l
+// GFX11: v_sub_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x66]
+
+v_sub_f16 v5.l, s105, v2.l
+// GFX11: v_sub_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x66]
+
+v_sub_f16 v5.l, vcc_lo, v2.l
+// GFX11: v_sub_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x66]
+
+v_sub_f16 v5.l, vcc_hi, v2.l
+// GFX11: v_sub_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x66]
-v_sub_f16 v5, v127, v2
-// GFX11: v_sub_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x66]
+v_sub_f16 v5.l, ttmp15, v2.l
+// GFX11: v_sub_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x66]
-v_sub_f16 v5, s1, v2
-// GFX11: v_sub_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x66]
+v_sub_f16 v5.l, m0, v2.l
+// GFX11: v_sub_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x66]
-v_sub_f16 v5, s105, v2
-// GFX11: v_sub_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x66]
+v_sub_f16 v5.l, exec_lo, v2.l
+// GFX11: v_sub_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x66]
-v_sub_f16 v5, vcc_lo, v2
-// GFX11: v_sub_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x66]
+v_sub_f16 v5.l, exec_hi, v2.l
+// GFX11: v_sub_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x66]
-v_sub_f16 v5, vcc_hi, v2
-// GFX11: v_sub_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x66]
+v_sub_f16 v5.l, null, v2.l
+// GFX11: v_sub_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x66]
-v_sub_f16 v5, ttmp15, v2
-// GFX11: v_sub_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x66]
+v_sub_f16 v5.l, -1, v2.l
+// GFX11: v_sub_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x66]
-v_sub_f16 v5, m0, v2
-// GFX11: v_sub_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x66]
+v_sub_f16 v5.l, 0.5, v2.l
+// GFX11: v_sub_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x66]
-v_sub_f16 v5, exec_lo, v2
-// GFX11: v_sub_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x66]
+v_sub_f16 v5.l, src_scc, v2.l
+// GFX11: v_sub_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x66]
-v_sub_f16 v5, exec_hi, v2
-// GFX11: v_sub_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x66]
+v_sub_f16 v127.l, 0xfe0b, v127.l
+// GFX11: v_sub_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
-v_sub_f16 v5, null, v2
-// GFX11: v_sub_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x66]
+v_sub_f16 v5.l, v1.h, v2.l
+// GFX11: v_sub_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x66]
-v_sub_f16 v5, -1, v2
-// GFX11: v_sub_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x66]
+v_sub_f16 v5.l, v127.h, v2.l
+// GFX11: v_sub_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x66]
-v_sub_f16 v5, 0.5, v2
-// GFX11: v_sub_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x66]
+v_sub_f16 v127.l, 0.5, v127.l
+// GFX11: v_sub_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x66]
-v_sub_f16 v5, src_scc, v2
-// GFX11: v_sub_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x66]
+v_sub_f16 v5.h, src_scc, v2.h
+// GFX11: v_sub_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x67]
-v_sub_f16 v127, 0xfe0b, v127
-// GFX11: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
+v_sub_f16 v127.h, 0xfe0b, v127.h
+// GFX11: v_sub_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00]
v_sub_f32 v5, v1, v2
// GFX11: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index 9d0a407a4cd5ec..325c240539fef0 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -116,47 +116,56 @@ v_add_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0
// W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
+v_add_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
-v_add_f16 v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff]
+v_add_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff]
-v_add_f16 v5, v1, v2 row_mirror
-// GFX11: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_mirror
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff]
-v_add_f16 v5, v1, v2 row_half_mirror
-// GFX11: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_half_mirror
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff]
-v_add_f16 v5, v1, v2 row_shl:1
-// GFX11: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_shl:1
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff]
-v_add_f16 v5, v1, v2 row_shl:15
-// GFX11: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_shl:15
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff]
-v_add_f16 v5, v1, v2 row_shr:1
-// GFX11: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_shr:1
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff]
-v_add_f16 v5, v1, v2 row_shr:15
-// GFX11: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_shr:15
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff]
-v_add_f16 v5, v1, v2 row_ror:1
-// GFX11: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_ror:1
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff]
-v_add_f16 v5, v1, v2 row_ror:15
-// GFX11: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_ror:15
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff]
-v_add_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff]
+v_add_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff]
-v_add_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01]
+v_add_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01]
-v_add_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13]
+v_add_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13]
-v_add_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30]
+v_add_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// GFX11: v_add_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30]
+
+v_add_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_add_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x5f,0x01,0x01]
+
+v_add_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_add_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x09,0x13]
+
+v_add_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_add_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xf5,0x30]
v_add_f32 v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff]
@@ -1666,47 +1675,56 @@ v_sub_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0
// W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff]
+v_sub_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff]
+
+v_sub_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff]
+
+v_sub_f16 v5.l, v1.l, v2.l row_mirror
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff]
+
+v_sub_f16 v5.l, v1.l, v2.l row_half_mirror
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff]
-v_sub_f16 v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_shl:1
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_mirror
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_shl:15
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_half_mirror
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_shr:1
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_shl:1
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_shr:15
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_shl:15
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_ror:1
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_shr:1
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_ror:15
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff]
-v_sub_f16 v5, v1, v2 row_shr:15
-// GFX11: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff]
+v_sub_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:0 ro...
[truncated]
|
arsenm
approved these changes
Dec 6, 2024
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This is a NFC change. Update mc test for v_add/sub_f16 in true16 format.
MC source change was done by previous patch and automatically enabled by t16 pesudo