[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode #119969
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| /// opcode are currently automatically considered to possibly raise | ||
| /// FP exceptions as well. | ||
| bool isTargetStrictFPOpcode() const { | ||
| return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE; |
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If you're going to start table generating the enum values for this, can you just set a high bit in the enum value for memory / strictfp?
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Unless I misunderstood you, it would require clearing these bits on any use of opcode, e.g. when creating a node or using the enum value as an index into the [generated] table.
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No, the enum values would just be larger values. For table compression you could implicitly know the chain status and truncate the table value
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I see your point now. This may work well for strict-fp opcodes, but it will be more difficult to implement for memory opcodes.
Not all memory opcodes will be generated, because some targets do not provide a tablegen description for all memory nodes. This means that some enum members will have to be assigned a value by hand, and this won't look pretty.
Some target that provide tablegen descriptons for memory nodes do not set SDNPMemOperand property on them. As a result, the generated enum values will not have the "memory bit" set, and there is no way to change the enum value included from a generated file.
In the future, we may want to add more properties (e.g., isBinOp), which I think is by itself a good justification for adding a separate field for them rather than encoding them in the opcode.
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Not all memory opcodes will be generated, because some targets do not provide a tablegen description for all memory nodes.
This sounds more like a bug. Your RFC sold not requiring targets to use this as a feature, but I'd consider it a defect. It would be better if targets were required to generate this kind of information from tablegen
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Not all memory opcodes will be generated, because some targets do not provide a tablegen description for all memory nodes.
This sounds more like a bug.
Depends how you look at it. It wasn't a bug before the proposed changes; targets were not required to describe all target-specific opcodes in *.td files.
Your RFC sold not requiring targets to use this as a feature, but I'd consider it a defect.
Yes, otherwise it wouldn't be sold. This feature/defect allows gradual migration.
It would be better if targets were required to generate this kind of information from tablegen
I guess we can do that once all in-tree targets have migrated. Probably need to give some time to downstream targets, too.
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backend:ARM
backend:AArch64
backend:AMDGPU
backend:RISC-V
backend:PowerPC
backend:SystemZ
backend:WebAssembly
backend:X86
backend:NVPTX
llvm:SelectionDAG
|
@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-aarch64 Author: Sergei Barannikov (s-barannikov) ChangesWith this change, targets are no longer required to put memory / strict-fp opcodes after special Part of #119709. Patch is 42.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119969.diff 42 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 0b6d155b6d161e..69820aed2137b5 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -1490,17 +1490,6 @@ enum NodeType {
BUILTIN_OP_END
};
-/// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
-/// which cannot raise FP exceptions should be less than this value.
-/// Those that do must not be less than this value.
-static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END + 400;
-
-/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
-/// which do not reference a specific memory location should be less than
-/// this value. Those that do must not be less than this value, and can
-/// be used with SelectionDAG::getMemIntrinsicNode.
-static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END + 500;
-
/// Whether this is bitwise logic opcode.
inline bool isBitwiseLogicOp(unsigned Opcode) {
return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index e97e01839f73b4..27cc1a2f963519 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1327,8 +1327,8 @@ class SelectionDAG {
/// Creates a MemIntrinsicNode that may produce a
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
- /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
- /// less than FIRST_TARGET_MEMORY_OPCODE.
+ /// INTRINSIC_W_CHAIN, or a target-specific memory-referencing opcode
+ // (see `SelectionDAGTargetInfo::isTargetMemoryOpcode`).
SDValue getMemIntrinsicNode(
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 61f3c6329efce8..46d8ae442bf2a2 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -210,7 +210,6 @@ class SDValue {
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
- inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
@@ -688,22 +687,6 @@ END_TWO_BYTE_PACK()
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
- /// Test if this node has a target-specific opcode that may raise
- /// FP exceptions (in the \<target\>ISD namespace and greater than
- /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
- /// opcode are currently automatically considered to possibly raise
- /// FP exceptions as well.
- bool isTargetStrictFPOpcode() const {
- return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
- }
-
- /// Test if this node has a target-specific
- /// memory-referencing opcode (in the \<target\>ISD namespace and
- /// greater than FIRST_TARGET_MEMORY_OPCODE).
- bool isTargetMemoryOpcode() const {
- return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
- }
-
/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }
@@ -1214,10 +1197,6 @@ inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
}
-inline bool SDValue::isTargetMemoryOpcode() const {
- return Node->isTargetMemoryOpcode();
-}
-
inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
}
@@ -1571,10 +1550,10 @@ class AtomicSDNode : public MemSDNode {
}
};
-/// This SDNode is used for target intrinsics that touch
-/// memory and need an associated MachineMemOperand. Its opcode may be
-/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
-/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
+/// This SDNode is used for target intrinsics that touch memory and need
+/// an associated MachineMemOperand. Its opcode may be INTRINSIC_VOID,
+/// INTRINSIC_W_CHAIN, PREFETCH, or a target-specific memory-referencing
+/// opcode (see `SelectionDAGTargetInfo::isTargetMemoryOpcode`).
class MemIntrinsicSDNode : public MemSDNode {
public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
index 720c9463867c34..ef5ae5dba58de4 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
@@ -35,6 +35,19 @@ class SelectionDAGTargetInfo {
SelectionDAGTargetInfo &operator=(const SelectionDAGTargetInfo &) = delete;
virtual ~SelectionDAGTargetInfo();
+ /// Returns true if a node with the given target-specific opcode has
+ /// a memory operand. Nodes with such opcodes can only be created with
+ /// `SelectionDAG::getMemIntrinsicNode`.
+ virtual bool isTargetMemoryOpcode(unsigned Opcode) const { return false; }
+
+ /// Returns true if a node with the given target-specific opcode has
+ /// strict floating-point semantics.
+ virtual bool isTargetStrictFPOpcode(unsigned Opcode) const { return false; }
+
+ /// Returns true if a node with the given target-specific opcode
+ /// may raise a floating-point exception.
+ virtual bool mayRaiseFPException(unsigned Opcode) const;
+
/// Emit target-specific code that performs a memcpy.
/// This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 34214550f3a12b..9d6430e697f241 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -8978,12 +8978,12 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
SDVTList VTList,
ArrayRef<SDValue> Ops, EVT MemVT,
MachineMemOperand *MMO) {
- assert((Opcode == ISD::INTRINSIC_VOID ||
- Opcode == ISD::INTRINSIC_W_CHAIN ||
- Opcode == ISD::PREFETCH ||
- (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
- (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
- "Opcode is not a memory-accessing opcode!");
+ assert(
+ (Opcode == ISD::INTRINSIC_VOID || Opcode == ISD::INTRINSIC_W_CHAIN ||
+ Opcode == ISD::PREFETCH ||
+ (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
+ Opcode >= ISD::BUILTIN_OP_END && TSI->isTargetMemoryOpcode(Opcode))) &&
+ "Opcode is not a memory-accessing opcode!");
// Memoize the node unless it returns a glue result.
MemIntrinsicSDNode *N;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 35aa7b87bc3b7f..527e851681b349 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -51,6 +51,7 @@
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/SwiftErrorValueTracking.h"
@@ -4395,8 +4396,10 @@ bool SelectionDAGISel::mayRaiseFPException(SDNode *N) const {
// For ISD opcodes, only StrictFP opcodes may raise an FP
// exception.
- if (N->isTargetOpcode())
- return N->isTargetStrictFPOpcode();
+ if (N->isTargetOpcode()) {
+ const SelectionDAGTargetInfo &TSI = CurDAG->getSelectionDAGInfo();
+ return TSI.mayRaiseFPException(N->getOpcode());
+ }
return N->isStrictFPOpcode();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
index 3a2df6f60593a9..0f3b36658f10ad 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
@@ -15,3 +15,9 @@
using namespace llvm;
SelectionDAGTargetInfo::~SelectionDAGTargetInfo() = default;
+
+bool SelectionDAGTargetInfo::mayRaiseFPException(unsigned Opcode) const {
+ // FIXME: All target memory opcodes are currently automatically considered
+ // to possibly raise FP exceptions. See rev. 63336795.
+ return isTargetStrictFPOpcode(Opcode) || isTargetMemoryOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index d51b36f7e49946..835c9381834724 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -477,7 +477,7 @@ enum NodeType : unsigned {
MSRR,
// Strict (exception-raising) floating point comparison
- STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ STRICT_FCMP,
STRICT_FCMPE,
// SME ZA loads and stores
@@ -485,7 +485,8 @@ enum NodeType : unsigned {
SME_ZA_STR,
// NEON Load/Store with post-increment base updates
- LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ LD2post = FIRST_MEMORY_OPCODE,
LD3post,
LD4post,
ST2post,
@@ -520,6 +521,7 @@ enum NodeType : unsigned {
STP,
STILP,
STNP,
+ LAST_MEMORY_OPCODE = STNP,
};
} // end namespace AArch64ISD
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
index c4d60a0cb4a118..9b946682b66228 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
@@ -23,6 +23,23 @@ static cl::opt<bool>
"to lower to librt functions"),
cl::init(true));
+bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ return Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= AArch64ISD::LAST_MEMORY_OPCODE;
+}
+
+bool AArch64SelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ switch (static_cast<AArch64ISD::NodeType>(Opcode)) {
+ default:
+ return false;
+ case AArch64ISD::STRICT_FCMP:
+ case AArch64ISD::STRICT_FCMPE:
+ case AArch64ISD::SME_ZA_LDR:
+ case AArch64ISD::SME_ZA_STR:
+ return true;
+ }
+}
+
SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
const SDLoc &DL, SDValue Chain,
SDValue Dst, SDValue SrcOrValue,
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
index 9d1f2e9cba846a..7efe49c7206555 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
@@ -19,6 +19,10 @@ namespace llvm {
class AArch64SelectionDAGInfo : public SelectionDAGTargetInfo {
public:
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
+
SDValue EmitMOPS(unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue SrcOrValue, SDValue Size,
Align Alignment, bool isVolatile,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 48e9af9fe507fb..f76acfe12e2953 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5555,7 +5555,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(PC_ADD_REL_OFFSET)
NODE_NAME_CASE(LDS)
NODE_NAME_CASE(DUMMY_CHAIN)
- case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
NODE_NAME_CASE(LOAD_D16_HI)
NODE_NAME_CASE(LOAD_D16_LO)
NODE_NAME_CASE(LOAD_D16_HI_I8)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 33991239a41209..c74dc7942f52c0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -546,8 +546,9 @@ enum NodeType : unsigned {
LDS,
DUMMY_CHAIN,
- FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
- LOAD_D16_HI,
+
+ FIRST_MEMORY_OPCODE,
+ LOAD_D16_HI = FIRST_MEMORY_OPCODE,
LOAD_D16_LO,
LOAD_D16_HI_I8,
LOAD_D16_HI_U8,
@@ -603,6 +604,7 @@ enum NodeType : unsigned {
BUFFER_ATOMIC_FMIN,
BUFFER_ATOMIC_FMAX,
BUFFER_ATOMIC_COND_SUB_U32,
+ LAST_MEMORY_OPCODE = BUFFER_ATOMIC_COND_SUB_U32,
};
} // End namespace AMDGPUISD
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
index 7bc651504e36d4..2941a48c78d941 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
@@ -7,7 +7,13 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUSelectionDAGInfo.h"
+#include "AMDGPUISelLowering.h"
using namespace llvm;
AMDGPUSelectionDAGInfo::~AMDGPUSelectionDAGInfo() = default;
+
+bool AMDGPUSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ return Opcode >= AMDGPUISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= AMDGPUISD::LAST_MEMORY_OPCODE;
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
index bb11a56da52596..3280be73b2fdf1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class AMDGPUSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~AMDGPUSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 4fa600e0cfcc40..cd663cebeab01f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -321,7 +321,8 @@ class VectorType;
CSINC, // Conditional select increment.
// Vector load N-element structure to all lanes:
- VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ VLD1DUP = FIRST_MEMORY_OPCODE,
VLD2DUP,
VLD3DUP,
VLD4DUP,
@@ -356,7 +357,8 @@ class VectorType;
// Load/Store of dual registers
LDRD,
- STRD
+ STRD,
+ LAST_MEMORY_OPCODE = STRD,
};
} // end namespace ARMISD
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
index e7ea10ff971a0c..a39487c318f8e0 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -30,6 +30,11 @@ cl::opt<TPLoop::MemTransfer> EnableMemtransferTPLoop(
"Allow (may be subject to certain conditions) "
"conversion of memcpy to TP loop.")));
+bool ARMSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ return Opcode >= ARMISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= ARMISD::LAST_MEMORY_OPCODE;
+}
+
// Emit, if possible, a specialized version of the given Libcall. Typically this
// means selecting the appropriately aligned version, but we also convert memset
// of 0 into memclr.
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
index 275b1c0f8dc017..d68150e66567ce 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
@@ -37,6 +37,8 @@ namespace ARM_AM {
class ARMSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index e245c056de6491..ae56bf7c8a2e72 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -247,7 +247,7 @@ class TargetRegisterClass;
DOUBLE_SELECT_I64,
// Load/Store Left/Right nodes.
- LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ LWL,
LWR,
SWL,
SWR,
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
index c24107bf639434..f6aea76b6fb0e4 100644
--- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
@@ -7,7 +7,24 @@
//===----------------------------------------------------------------------===//
#include "MipsSelectionDAGInfo.h"
+#include "MipsISelLowering.h"
using namespace llvm;
MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default;
+
+bool MipsSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ switch (static_cast<MipsISD::NodeType>(Opcode)) {
+ default:
+ return false;
+ case MipsISD::LWL:
+ case MipsISD::LWR:
+ case MipsISD::SWL:
+ case MipsISD::SWR:
+ case MipsISD::LDL:
+ case MipsISD::LDR:
+ case MipsISD::SDL:
+ case MipsISD::SDR:
+ return true;
+ }
+}
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
index bccd924a30e711..934cd2e056595d 100644
--- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class MipsSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~MipsSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index c8b589ae39413e..f7c59973f8d1a5 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -70,7 +70,8 @@ enum NodeType : unsigned {
BrxEnd,
Dummy,
- LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ LoadV2 = FIRST_MEMORY_OPCODE,
LoadV4,
LDUV2, // LDU.v2
LDUV4, // LDU.v4
@@ -443,7 +444,8 @@ enum NodeType : unsigned {
Suld3DV2I64Zero,
Suld3DV4I8Zero,
Suld3DV4I16Zero,
- Suld3DV4I32Zero
+ Suld3DV4I32Zero,
+ LAST_MEMORY_OPCODE = Suld3DV4I32Zero,
};
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
index 9c26f310bbf653..d2035c6f8166f2 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
@@ -7,7 +7,13 @@
//===----------------------------------------------------------------------===//
#include "NVPTXSelectionDAGInfo.h"
+#include "NVPTXISelLowering.h"
using namespace llvm;
NVPTXSelectionDAGInfo::~NVPTXSelectionDAGInfo() = default;
+
+bool NVPTXSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ return Opcode >= NVPTXISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= NVPTXISD::LAST_MEMORY_OPCODE;
+}
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
index 6b04d78ca96878..9d69f48026c790 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class NVPTXSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~NVPTXSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 8f41fc107a6918..7ee1b9bbbce511 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -36,14 +36,11 @@ namespace llvm {
namespace PPCISD {
- // When adding a NEW PPCISD node please add it to the correct position in
- // the enum. The order of elements in this enum matters!
- // Values that are added after this entry:
- // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
- ...
[truncated]
|
RKSimon
reviewed
Dec 16, 2024
davemgreen
reviewed
Dec 16, 2024
Comment on lines
37
to
38
| case AArch64ISD::SME_ZA_LDR: | ||
| case AArch64ISD::SME_ZA_STR: |
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Can you remove these two from here, as in #120091? If so the Arm/AArch64 parts look Ok to me.
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I've merged that commit.
Note that these opcodes are not included in *MEMORY_OPCODE range -- those are supposed to be used with getMemIntrinsicNode (other than that, there isn't much difference).
…tualize-memory-strictfp
|
Thank you all for taking a look |
RKSimon
reviewed
Dec 19, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/11820 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/81/builds/3270 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/141/builds/4898 Here is the relevant piece of the build log for the reference |
github-actions bot
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…tMemoryOpcode (#119969) With this change, targets are no longer required to put memory / strict-fp opcodes after special `ISD::FIRST_TARGET_MEMORY_OPCODE`/`ISD::FIRST_TARGET_STRICTFP_OPCODE` markers. This will also allow autogenerating `isTargetMemoryOpcode`/`isTargetStrictFPOpcode (#119709). Pull Request: llvm/llvm-project#119969
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Feb 7, 2025
Local branch amd-gfx 6cc1d54 Merged main:44514316bd5e into amd-gfx:d5f5db91c4b0 Remote branch main 9ae92d7 [SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (llvm#119969)
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With this change, targets are no longer required to put memory / strict-fp opcodes after special
ISD::FIRST_TARGET_MEMORY_OPCODE/ISD::FIRST_TARGET_STRICTFP_OPCODEmarkers.This will also allow autogenerating
isTargetMemoryOpcode/isTargetStrictFPOpcode.Part of #119709.