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[X86] Put R20/R21/R28/R29 later in GR64 list #120510

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Merged
merged 2 commits into from
Dec 19, 2024
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[X86] Put R20/R21/R28/R29 later in GR64 list #120510

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[X86] Put R20/R21/R28/R29 later in GR64 list
fzou1 Dec 17, 2024
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fzou1 Dec 19, 2024
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26 changes: 13 additions & 13 deletions llvm/lib/Target/X86/X86RegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -541,18 +541,18 @@ def SSP : X86Reg<"ssp", 0>;
// R12, R13, R14, and R15 for X86-64) are callee-save registers.
// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
// R8B, ... R15B.
// Allocate R12 and R13 last, as these require an extra byte when
// encoded in x86_64 instructions.
// Allocate R12, R13, R20, R21, R28 and R29 last, as these require an extra byte
// when encoded in x86_64 instructions.
// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
// 64-bit mode. The main complication is that they cannot be encoded in an
// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
// cannot be encoded.
def GR8 : RegisterClass<"X86", [i8], 8,
(add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R20B,
R21B, R22B, R23B, R24B, R25B, R26B, R27B, R28B, R29B,
R30B, R31B, R14B, R15B, R12B, R13B)> {
R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R22B,
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Update the comment above which refers to R12/R13 being allocated last

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Updated. Thank you.

R23B, R24B, R25B, R26B, R27B, R30B, R31B, R14B,
R15B, R12B, R13B, R20B, R21B, R28B, R29B)> {
let AltOrders = [(sub GR8, AH, BH, CH, DH)];
let AltOrderSelect = [{
return MF.getSubtarget<X86Subtarget>().is64Bit();
Expand All @@ -567,9 +567,9 @@ def GRH8 : RegisterClass<"X86", [i8], 8,
R26BH, R27BH, R28BH, R29BH, R30BH, R31BH)>;
def GR16 : RegisterClass<"X86", [i16], 16,
(add AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W,
R11W, R16W, R17W, R18W, R19W, R20W, R21W, R22W, R23W,
R24W, R25W, R26W, R27W, R28W, R29W, R30W, R31W, R14W,
R15W, R12W, R13W)>;
R11W, R16W, R17W, R18W, R19W, R22W, R23W, R24W,
R25W, R26W, R27W, R30W, R31W, R14W, R15W, R12W,
R13W, R20W, R21W, R28W, R29W)>;

let isAllocatable = 0 in
def GRH16 : RegisterClass<"X86", [i16], 16,
Expand All @@ -579,9 +579,9 @@ def GRH16 : RegisterClass<"X86", [i16], 16,
R25WH, R26WH, R27WH, R28WH, R29WH, R30WH, R31WH)>;
def GR32 : RegisterClass<"X86", [i32], 32,
(add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D,
R10D, R11D, R16D, R17D, R18D, R19D, R20D, R21D, R22D,
R23D, R24D, R25D, R26D, R27D, R28D, R29D, R30D, R31D,
R14D, R15D, R12D, R13D)>;
R10D, R11D, R16D, R17D, R18D, R19D, R22D, R23D,
R24D, R25D, R26D, R27D, R30D, R31D, R14D, R15D,
R12D, R13D, R20D, R21D, R28D, R29D)>;

// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
// RIP isn't really a register and it can't be used anywhere except in an
Expand All @@ -590,8 +590,8 @@ def GR32 : RegisterClass<"X86", [i32], 32,
// tests because of the inclusion of RIP in this register class.
def GR64 : RegisterClass<"X86", [i64], 64,
(add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
R30, R31, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,
R14, R15, R12, R13, R20, R21, R28, R29, RBP, RSP, RIP)>;

// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
// emitting code for intrinsics, which use implict input registers.
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