[AMDGPU] Add commute for some VOP3 inst #121326
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@@ -2749,6 +2749,20 @@ static MachineInstr *swapRegAndNonRegOperand(MachineInstr &MI, | |
| return &MI; | ||
| } | ||
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| static MachineInstr *swapInlineConstOperands(MachineInstr &MI, | ||
| MachineOperand &NonRegOp1, | ||
| MachineOperand &NonRegOp2) { | ||
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| auto TargetFlags = NonRegOp1.getTargetFlags(); | ||
| auto NonRegVal = NonRegOp1.getImm(); | ||
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| NonRegOp1.setImm(NonRegOp2.getImm()); | ||
| NonRegOp2.setImm(NonRegVal); | ||
| NonRegOp1.setTargetFlags(NonRegOp2.getTargetFlags()); | ||
| NonRegOp2.setTargetFlags(TargetFlags); | ||
| return &MI; | ||
| } | ||
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| MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, | ||
| unsigned Src0Idx, | ||
| unsigned Src1Idx) const { | ||
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@@ -2785,6 +2799,9 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, | |
| } else if (!Src0.isReg() && Src1.isReg()) { | ||
| if (isOperandLegal(MI, Src1Idx, &Src0)) | ||
| CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0); | ||
| } else if (isInlineConstant(Src0) && isInlineConstant(Src1)) { | ||
| if (isOperandLegal(MI, Src1Idx, &Src0)) | ||
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There was a problem hiding this comment. At least one of these isInlineConstant checks is redundant with the isOperandLegal check There was a problem hiding this comment. Hi @arsenm , sorry for replying late, it took me long time to investigate the By testing, one of the operand is inline constant and It is true for VOP that if Src1 is inline constant, then Src0 is also has to be an inline constant. But the reason for that is if I think this may be not consistent with ISA on section "6.12.1 Instruction Inputs" saying:
There was a problem hiding this comment. BTW, the isOperandLegal check may also be necessary, because some of the operand type cannot use inline constant, e.g. second operand of |
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| CommutedMI = swapInlineConstOperands(MI, Src0, Src1); | ||
| } else { | ||
| // FIXME: Found two non registers to commute. This does happen. | ||
| return nullptr; | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -1,12 +1,11 @@ | ||
| # RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s | ||
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| --- | ||
| name: test_machine_cse_op_sel | ||
| body: | | ||
| ; GCN-LABEL: name: test_machine_cse_op_sel | ||
| ; GCN: %2:vgpr_32 = V_ADD_NC_U16_e64 0, %0, 0, %1, 1, 0, implicit $mode, implicit $exec | ||
| ; GCN-NEXT: DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %2, %2, 0, 1, 0, implicit $exec | ||
| bb.0: | ||
| %0:vgpr_32 = IMPLICIT_DEF | ||
| %1:vgpr_32 = IMPLICIT_DEF | ||
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@@ -15,3 +14,14 @@ body: | | |
| DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %2, %3, 0, 1, 0, implicit $exec | ||
| ... | ||
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| --- | ||
| name: test_machine_cse_op_inline_const | ||
| body: | | ||
| ; GCN-LABEL: name: test_machine_cse_op_inline_const | ||
| ; GCN: %0:vgpr_32 = V_ADD_NC_U16_e64 0, 64, 0, -3, 1, 0, implicit $mode, implicit $exec | ||
| ; GCN-NEXT: DS_WRITE2_B32_gfx9 undef %2:vgpr_32, %0, %0, 0, 1, 0, implicit $exec | ||
| bb.0: | ||
| %1:vgpr_32 = V_ADD_NC_U16_e64 0, 64, 0, -3, 1, 0, implicit $mode, implicit $exec | ||
| %2:vgpr_32 = V_ADD_NC_U16_e64 0, -3, 0, 64, 1, 0, implicit $mode, implicit $exec | ||
| DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %1, %2, 0, 1, 0, implicit $exec | ||
| ... | ||
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There was a problem hiding this comment. There should be a dedicated commute test for every changed opcode like this. What about the _e32 forms? There was a problem hiding this comment. Hi, for |
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