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[X86][AVX10.2] Lower fmininum/fmaximum to VMINMAX* #121373

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Merged
merged 1 commit into from
Jan 2, 2025
Merged

[X86][AVX10.2] Lower fmininum/fmaximum to VMINMAX* #121373

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18 changes: 18 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2442,6 +2442,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FSQRT, VT, Legal);
setOperationAction(ISD::FMA, VT, Legal);
setOperationAction(ISD::SETCC, VT, Custom);
setOperationAction(ISD::FMINIMUM, VT, Custom);
setOperationAction(ISD::FMAXIMUM, VT, Custom);
}
if (Subtarget.hasAVX10_2_512()) {
setOperationAction(ISD::FADD, MVT::v32bf16, Legal);
Expand All @@ -2451,6 +2453,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FSQRT, MVT::v32bf16, Legal);
setOperationAction(ISD::FMA, MVT::v32bf16, Legal);
setOperationAction(ISD::SETCC, MVT::v32bf16, Custom);
setOperationAction(ISD::FMINIMUM, MVT::v32bf16, Custom);
setOperationAction(ISD::FMAXIMUM, MVT::v32bf16, Custom);
}
for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) {
setCondCodeAction(ISD::SETOEQ, VT, Custom);
Expand Down Expand Up @@ -28842,6 +28846,20 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
SDValue X = Op.getOperand(0);
SDValue Y = Op.getOperand(1);
SDLoc DL(Op);
if (Subtarget.hasAVX10_2() && TLI.isTypeLegal(VT)) {
unsigned Opc = 0;
if (VT.isVector())
Opc = X86ISD::VMINMAX;
else if (VT == MVT::f16 || VT == MVT::f32 || VT == MVT::f64)
Opc = X86ISD::VMINMAXS;

if (Opc) {
SDValue Imm =
DAG.getTargetConstant(Op.getOpcode() == ISD::FMAXIMUM, DL, MVT::i32);
return DAG.getNode(Opc, DL, VT, X, Y, Imm, Op->getFlags());
}
}

uint64_t SizeInBits = VT.getScalarSizeInBits();
APInt PreferredZero = APInt::getZero(SizeInBits);
APInt OppositeZero = PreferredZero;
Expand Down
52 changes: 33 additions & 19 deletions llvm/lib/Target/X86/X86InstrAVX10.td
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Original file line number Diff line number Diff line change
Expand Up @@ -403,28 +403,42 @@ multiclass avx10_minmax_scalar<string OpStr, X86VectorVTInfo _, SDNode OpNode,
SDNode OpNodeSAE> {
let ExeDomain = _.ExeDomain, Predicates = [HasAVX10_2] in {
let mayRaiseFPException = 1 in {
defm rri : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
(ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>,
Sched<[WriteFMAX]>;

defm rmi : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),
(ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
(i32 timm:$src3)))>,
let isCodeGenOnly = 1 in {
def rri : AVX512Ii8<0x53, MRMSrcReg, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
!strconcat(OpStr, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
[(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2, (i32 timm:$src3)))]>,
Sched<[WriteFMAX]>;

def rmi : AVX512Ii8<0x53, MRMSrcMem, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
!strconcat(OpStr, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
[(set _.FRC:$dst, (OpNode _.FRC:$src1, (_.ScalarLdFrag addr:$src2),
(i32 timm:$src3)))]>,
Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
}
defm rri_Int : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
(ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>,
Sched<[WriteFMAX]>;

defm rmi_Int : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),
(ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
(i32 timm:$src3)))>,
Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
}
let Uses = []<Register>, mayRaiseFPException = 0 in
defm rrib : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
(ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
OpStr, "$src3, {sae}, $src2, $src1",
"$src1, $src2, {sae}, $src3",
(_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>,
Sched<[WriteFMAX]>, EVEX_B;
defm rrib_Int : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
(ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
OpStr, "$src3, {sae}, $src2, $src1",
"$src1, $src2, {sae}, $src3",
(_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>,
Sched<[WriteFMAX]>, EVEX_B;
}
}

Expand Down
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