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release/20.x: Revert Do not use private as the default AS for when generic is available (#112442)" #127771

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Merged
merged 1 commit into from
Feb 25, 2025
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release/20.x: Revert Do not use private as the default AS for when generic is available (#112442)" #127771

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6 changes: 3 additions & 3 deletions clang/lib/Basic/Targets/AMDGPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -261,9 +261,9 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,
void AMDGPUTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
TargetInfo::adjust(Diags, Opts);
// ToDo: There are still a few places using default address space as private
// address space in OpenCL, which needs to be cleaned up, then the references
// to OpenCL can be removed from the following line.
setAddressSpaceMap((Opts.OpenCL && !Opts.OpenCLGenericAddressSpace) ||
// address space in OpenCL, which needs to be cleaned up, then Opts.OpenCL
// can be removed from the following line.
setAddressSpaceMap(/*DefaultIsPrivate=*/Opts.OpenCL ||
!isAMDGCN(getTriple()));
}

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3 changes: 1 addition & 2 deletions clang/lib/CodeGen/CGBlocks.cpp
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Expand Up @@ -1396,8 +1396,7 @@ void CodeGenFunction::setBlockContextParameter(const ImplicitParamDecl *D,
DI->setLocation(D->getLocation());
DI->EmitDeclareOfBlockLiteralArgVariable(
*BlockInfo, D->getName(), argNum,
cast<llvm::AllocaInst>(alloc.getPointer()->stripPointerCasts()),
Builder);
cast<llvm::AllocaInst>(alloc.getPointer()), Builder);
}
}

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11 changes: 2 additions & 9 deletions clang/lib/CodeGen/CGBuiltin.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6092,13 +6092,8 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
/*IndexTypeQuals=*/0);
auto Tmp = CreateMemTemp(SizeArrayTy, "block_sizes");
llvm::Value *TmpPtr = Tmp.getPointer();
// The EmitLifetime* pair expect a naked Alloca as their last argument,
// however for cases where the default AS is not the Alloca AS, Tmp is
// actually the Alloca ascasted to the default AS, hence the
// stripPointerCasts()
llvm::Value *Alloca = TmpPtr->stripPointerCasts();
llvm::Value *TmpSize = EmitLifetimeStart(
CGM.getDataLayout().getTypeAllocSize(Tmp.getElementType()), Alloca);
CGM.getDataLayout().getTypeAllocSize(Tmp.getElementType()), TmpPtr);
llvm::Value *ElemPtr;
// Each of the following arguments specifies the size of the corresponding
// argument passed to the enqueued block.
Expand All @@ -6114,9 +6109,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
Builder.CreateAlignedStore(
V, GEP, CGM.getDataLayout().getPrefTypeAlign(SizeTy));
}
// Return the Alloca itself rather than a potential ascast as this is only
// used by the paired EmitLifetimeEnd.
return std::tie(ElemPtr, TmpSize, Alloca);
return std::tie(ElemPtr, TmpSize, TmpPtr);
};

// Could have events and/or varargs.
Expand Down
181 changes: 120 additions & 61 deletions clang/test/CodeGen/scoped-fence-ops.c
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@@ -1,8 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \
// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
// RUN: -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN-CL12 %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \
// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN-CL20 %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \
// RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \
Expand Down Expand Up @@ -30,34 +30,62 @@ void fe1a() {
__scoped_atomic_thread_fence(__ATOMIC_RELEASE, __MEMORY_SCOPE_WRKGRP);
}

// AMDGCN-LABEL: define hidden void @fe1b(
// AMDGCN-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
// AMDGCN-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-NEXT: [[ORD_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ORD_ADDR]] to ptr
// AMDGCN-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR_ASCAST]], align 4
// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR_ASCAST]], align 4
// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-NEXT: i32 1, label %[[ACQUIRE:.*]]
// AMDGCN-NEXT: i32 2, label %[[ACQUIRE]]
// AMDGCN-NEXT: i32 3, label %[[RELEASE:.*]]
// AMDGCN-NEXT: i32 4, label %[[ACQREL:.*]]
// AMDGCN-NEXT: i32 5, label %[[SEQCST:.*]]
// AMDGCN-NEXT: ]
// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-NEXT: ret void
// AMDGCN: [[ACQUIRE]]:
// AMDGCN-NEXT: fence syncscope("workgroup") acquire
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[RELEASE]]:
// AMDGCN-NEXT: fence syncscope("workgroup") release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[ACQREL]]:
// AMDGCN-NEXT: fence syncscope("workgroup") acq_rel
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[SEQCST]]:
// AMDGCN-NEXT: fence syncscope("workgroup") seq_cst
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12-LABEL: define hidden void @fe1b(
// AMDGCN-CL12-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
// AMDGCN-CL12-NEXT: [[ENTRY:.*:]]
// AMDGCN-CL12-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-CL12-NEXT: [[ORD_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ORD_ADDR]] to ptr
// AMDGCN-CL12-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR_ASCAST]], align 4
// AMDGCN-CL12-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR_ASCAST]], align 4
// AMDGCN-CL12-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-CL12-NEXT: i32 1, label %[[ACQUIRE:.*]]
// AMDGCN-CL12-NEXT: i32 2, label %[[ACQUIRE]]
// AMDGCN-CL12-NEXT: i32 3, label %[[RELEASE:.*]]
// AMDGCN-CL12-NEXT: i32 4, label %[[ACQREL:.*]]
// AMDGCN-CL12-NEXT: i32 5, label %[[SEQCST:.*]]
// AMDGCN-CL12-NEXT: ]
// AMDGCN-CL12: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-CL12-NEXT: ret void
// AMDGCN-CL12: [[ACQUIRE]]:
// AMDGCN-CL12-NEXT: fence syncscope("workgroup") acquire
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[RELEASE]]:
// AMDGCN-CL12-NEXT: fence syncscope("workgroup") release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[ACQREL]]:
// AMDGCN-CL12-NEXT: fence syncscope("workgroup") acq_rel
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[SEQCST]]:
// AMDGCN-CL12-NEXT: fence syncscope("workgroup") seq_cst
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
//
// AMDGCN-CL20-LABEL: define hidden void @fe1b(
// AMDGCN-CL20-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
// AMDGCN-CL20-NEXT: [[ENTRY:.*:]]
// AMDGCN-CL20-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-CL20-NEXT: store i32 [[ORD]], ptr addrspace(5) [[ORD_ADDR]], align 4
// AMDGCN-CL20-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[ORD_ADDR]], align 4
// AMDGCN-CL20-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-CL20-NEXT: i32 1, label %[[ACQUIRE:.*]]
// AMDGCN-CL20-NEXT: i32 2, label %[[ACQUIRE]]
// AMDGCN-CL20-NEXT: i32 3, label %[[RELEASE:.*]]
// AMDGCN-CL20-NEXT: i32 4, label %[[ACQREL:.*]]
// AMDGCN-CL20-NEXT: i32 5, label %[[SEQCST:.*]]
// AMDGCN-CL20-NEXT: ]
// AMDGCN-CL20: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-CL20-NEXT: ret void
// AMDGCN-CL20: [[ACQUIRE]]:
// AMDGCN-CL20-NEXT: fence syncscope("workgroup") acquire
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[RELEASE]]:
// AMDGCN-CL20-NEXT: fence syncscope("workgroup") release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[ACQREL]]:
// AMDGCN-CL20-NEXT: fence syncscope("workgroup") acq_rel
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[SEQCST]]:
// AMDGCN-CL20-NEXT: fence syncscope("workgroup") seq_cst
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
//
// SPIRV-LABEL: define hidden spir_func void @fe1b(
// SPIRV-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
Expand Down Expand Up @@ -119,37 +147,68 @@ void fe1b(int ord) {
__scoped_atomic_thread_fence(ord, __MEMORY_SCOPE_WRKGRP);
}

// AMDGCN-LABEL: define hidden void @fe1c(
// AMDGCN-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
// AMDGCN-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-NEXT: [[SCOPE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCOPE_ADDR]] to ptr
// AMDGCN-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR_ASCAST]], align 4
// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR_ASCAST]], align 4
// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
// AMDGCN-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
// AMDGCN-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
// AMDGCN-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
// AMDGCN-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
// AMDGCN-NEXT: ]
// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-NEXT: ret void
// AMDGCN: [[DEVICE_SCOPE]]:
// AMDGCN-NEXT: fence syncscope("agent") release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[SYSTEM_SCOPE]]:
// AMDGCN-NEXT: fence release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[WORKGROUP_SCOPE]]:
// AMDGCN-NEXT: fence syncscope("workgroup") release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[WAVEFRONT_SCOPE]]:
// AMDGCN-NEXT: fence syncscope("wavefront") release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN: [[SINGLE_SCOPE]]:
// AMDGCN-NEXT: fence syncscope("singlethread") release
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12-LABEL: define hidden void @fe1c(
// AMDGCN-CL12-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
// AMDGCN-CL12-NEXT: [[ENTRY:.*:]]
// AMDGCN-CL12-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-CL12-NEXT: [[SCOPE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCOPE_ADDR]] to ptr
// AMDGCN-CL12-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR_ASCAST]], align 4
// AMDGCN-CL12-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR_ASCAST]], align 4
// AMDGCN-CL12-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-CL12-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
// AMDGCN-CL12-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
// AMDGCN-CL12-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
// AMDGCN-CL12-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
// AMDGCN-CL12-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
// AMDGCN-CL12-NEXT: ]
// AMDGCN-CL12: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-CL12-NEXT: ret void
// AMDGCN-CL12: [[DEVICE_SCOPE]]:
// AMDGCN-CL12-NEXT: fence syncscope("agent") release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[SYSTEM_SCOPE]]:
// AMDGCN-CL12-NEXT: fence release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[WORKGROUP_SCOPE]]:
// AMDGCN-CL12-NEXT: fence syncscope("workgroup") release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[WAVEFRONT_SCOPE]]:
// AMDGCN-CL12-NEXT: fence syncscope("wavefront") release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL12: [[SINGLE_SCOPE]]:
// AMDGCN-CL12-NEXT: fence syncscope("singlethread") release
// AMDGCN-CL12-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
//
// AMDGCN-CL20-LABEL: define hidden void @fe1c(
// AMDGCN-CL20-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
// AMDGCN-CL20-NEXT: [[ENTRY:.*:]]
// AMDGCN-CL20-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
// AMDGCN-CL20-NEXT: store i32 [[SCOPE]], ptr addrspace(5) [[SCOPE_ADDR]], align 4
// AMDGCN-CL20-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[SCOPE_ADDR]], align 4
// AMDGCN-CL20-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
// AMDGCN-CL20-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
// AMDGCN-CL20-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
// AMDGCN-CL20-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
// AMDGCN-CL20-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
// AMDGCN-CL20-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
// AMDGCN-CL20-NEXT: ]
// AMDGCN-CL20: [[ATOMIC_SCOPE_CONTINUE]]:
// AMDGCN-CL20-NEXT: ret void
// AMDGCN-CL20: [[DEVICE_SCOPE]]:
// AMDGCN-CL20-NEXT: fence syncscope("agent") release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[SYSTEM_SCOPE]]:
// AMDGCN-CL20-NEXT: fence release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[WORKGROUP_SCOPE]]:
// AMDGCN-CL20-NEXT: fence syncscope("workgroup") release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[WAVEFRONT_SCOPE]]:
// AMDGCN-CL20-NEXT: fence syncscope("wavefront") release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
// AMDGCN-CL20: [[SINGLE_SCOPE]]:
// AMDGCN-CL20-NEXT: fence syncscope("singlethread") release
// AMDGCN-CL20-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
//
// SPIRV-LABEL: define hidden spir_func void @fe1c(
// SPIRV-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
Expand Down
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