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[GlobalISel] Introduce G_POISON #127825

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[GlobalISel] Introduce G_POISON #127825

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0d07595
[GlobalISel] Introduce `G_POISON`
mtsokol Feb 19, 2025
a8569f2
Adjust targets for `G_POISON`
mtsokol Apr 20, 2025
59a800d
First patch for failing tests
mtsokol Apr 20, 2025
a8cc507
Remove combine logic
mtsokol Apr 20, 2025
c6b0e4e
another patch
mtsokol Apr 20, 2025
b62284a
Trial - update AMDGPU tests
mtsokol Apr 20, 2025
2af2004
Further improvements
mtsokol Apr 22, 2025
386e424
Further work
mtsokol Apr 22, 2025
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22 changes: 16 additions & 6 deletions llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -455,7 +455,8 @@ bool CombinerHelper::matchCombineShuffleConcat(
return false;
}
if (!isLegalOrBeforeLegalizer(
{TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}))
{TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}) ||
!isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {ConcatSrcTy}}))
return false;
Ops.push_back(0);
} else if (Mask[i] % ConcatSrcNumElt == 0) {
Expand Down Expand Up @@ -2733,7 +2734,8 @@ void CombinerHelper::applyCombineTruncOfShift(
bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) const {
return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
return MO.isReg() &&
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
(getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI));
Comment on lines +2739 to +2740
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Can you add a fixme? We shouldn't look up copy chains twice just to check 2 opcodes. We should delete getOpcodeDef as a helper, it's not good

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Done! In the next patch I can come up with some helpers where getOpcodeDef accepts a set of opcodes.

});
}

Expand All @@ -2746,7 +2748,8 @@ bool CombinerHelper::matchAnyExplicitUseIsPoison(MachineInstr &MI) const {
bool CombinerHelper::matchAllExplicitUsesAreUndef(MachineInstr &MI) const {
return all_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
return !MO.isReg() ||
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI);
});
}

Expand All @@ -2766,6 +2769,8 @@ bool CombinerHelper::matchUndefShuffleVectorMask(MachineInstr &MI) const {
bool CombinerHelper::matchUndefStore(MachineInstr &MI) const {
assert(MI.getOpcode() == TargetOpcode::G_STORE);
return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
MRI) ||
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
MRI);
}

Expand All @@ -2777,6 +2782,8 @@ bool CombinerHelper::matchPoisonStore(MachineInstr &MI) const {
bool CombinerHelper::matchUndefSelectCmp(MachineInstr &MI) const {
assert(MI.getOpcode() == TargetOpcode::G_SELECT);
return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
MRI) ||
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
MRI);
}

Expand Down Expand Up @@ -3010,7 +3017,8 @@ bool CombinerHelper::matchOperandIsUndef(MachineInstr &MI,
unsigned OpIdx) const {
MachineOperand &MO = MI.getOperand(OpIdx);
return MO.isReg() &&
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
(getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI));
}

bool CombinerHelper::matchOperandIsPoison(MachineInstr &MI,
Expand Down Expand Up @@ -7960,10 +7968,12 @@ bool CombinerHelper::matchShuffleDisjointMask(MachineInstr &MI,
auto &Shuffle = cast<GShuffleVector>(MI);
// If any of the two inputs is already undef, don't check the mask again to
// prevent infinite loop
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc1Reg(), MRI))
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc1Reg(), MRI) ||
getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc1Reg(), MRI))
return false;

if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc2Reg(), MRI))
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc2Reg(), MRI) ||
getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc2Reg(), MRI))
return false;

const LLT DstTy = MRI.getType(Shuffle.getReg(0));
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8454,16 +8454,16 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {

auto OutPos = MIRBuilder.buildConstant(IdxTy, 0);

bool HasPassthru =
MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_POISON;
auto *PassthruMI = MRI.getVRegDef(Passthru);
bool HasPassthru = PassthruMI->getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
PassthruMI->getOpcode() != TargetOpcode::G_POISON;

if (HasPassthru)
MIRBuilder.buildStore(Passthru, StackPtr, PtrInfo, VecAlign);

Register LastWriteVal;
std::optional<APInt> PassthruSplatVal =
isConstantOrConstantSplatVector(*MRI.getVRegDef(Passthru), MRI);
isConstantOrConstantSplatVector(*PassthruMI, MRI);

if (PassthruSplatVal.has_value()) {
LastWriteVal =
Expand Down
34 changes: 15 additions & 19 deletions llvm/lib/Target/AArch64/AArch64Combine.td
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Original file line number Diff line number Diff line change
Expand Up @@ -131,23 +131,19 @@ def ext: GICombineRule <
(apply [{ applyEXT(*${root}, ${matchinfo}); }])
>;

def fullrev: GICombineRule <
(defs root:$root, shuffle_matchdata:$matchinfo),
(match (G_IMPLICIT_DEF $src2),
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
${mask}.getShuffleMask().size()); }]),
(apply [{ applyFullRev(*${root}, MRI); }])
>;

def fullrevpoison: GICombineRule <
(defs root:$root, shuffle_matchdata:$matchinfo),
(match (G_POISON $src2),
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
def undef_or_poison_op
: GICombinePatFrag<(outs root:$src2), (ins),
!foreach(op, [G_IMPLICIT_DEF, G_POISON],
(pattern(op $src2)))>;

def fullrev
: GICombineRule<
(defs root:$root, shuffle_matchdata:$matchinfo),
(match(undef_or_poison_op $src2),
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
${mask}.getShuffleMask().size()); }]),
(apply [{ applyFullRev(*${root}, MRI); }])
>;
(apply [{ applyFullRev(*${root}, MRI); }])>;

def insertelt_nonconst: GICombineRule <
(defs root:$root, shuffle_matchdata:$matchinfo),
Expand Down Expand Up @@ -181,9 +177,9 @@ def form_duplane : GICombineRule <
(apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
>;

def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn, fullrev,
fullrevpoison, form_duplane,
shuf_to_ins]>;
def shuffle_vector_lowering
: GICombineGroup<[dup, rev, ext, zip, uzp, trn, fullrev, form_duplane,
shuf_to_ins]>;

// Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's
def vector_unmerge_lowering : GICombineRule <
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
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Expand Up @@ -710,7 +710,7 @@ define <3 x i16> @v3i16_func_void() #0 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_POISON
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load (<3 x s16>) from `ptr addrspace(1) poison`, align 8, addrspace 1)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<3 x s16>)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_POISON
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[DEF1]](s16)
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)
; CHECK-NEXT: $vgpr0 = COPY [[UV3]](<2 x s16>)
Expand Down Expand Up @@ -753,7 +753,7 @@ define <5 x i16> @v5i16_func_void() #0 {
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<5 x s16>) = G_LOAD [[LOAD]](p1) :: (load (<5 x s16>) from %ir.ptr, align 16, addrspace 1)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD1]](<5 x s16>)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_POISON
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[DEF1]](s16)
; CHECK-NEXT: [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<6 x s16>)
; CHECK-NEXT: $vgpr0 = COPY [[UV5]](<2 x s16>)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
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Expand Up @@ -39,7 +39,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_POISON
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
Expand Down
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