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[Xtensa] Implement Xtensa MAC16 Option. #130004

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Merged
merged 2 commits into from
Mar 10, 2025
Merged

[Xtensa] Implement Xtensa MAC16 Option. #130004

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298aedd
[Xtensa] Implement Xtensa MAC16 Option.
andreisfr Mar 6, 2025
f1e3f33
[Xtensa] Minor fixes.
andreisfr Mar 6, 2025
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44 changes: 43 additions & 1 deletion llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -73,8 +73,50 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}

static const unsigned MRDecoderTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2,
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MCPhysReg

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Thank you very much for comments. Fixed

Xtensa::M3};

static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
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Start with lowercase

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Sorry, am I understand correctly that DecodeMRRegisterStatus function name should start with lowercase? It seems that this name is generated by tablegen.

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oh, ok

uint64_t Address,
const void *Decoder) {
if (RegNo >= std::size(MRDecoderTable))
return MCDisassembler::Fail;

unsigned Reg = MRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static const unsigned MR01DecoderTable[] = {Xtensa::M0, Xtensa::M1};

static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 2)
return MCDisassembler::Fail;

unsigned Reg = MR01DecoderTable[RegNo];
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MCRegister

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Fixed

Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static const unsigned MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
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MCPhysReg

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Fixed


static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
if ((RegNo < 2) || (RegNo > 3))
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Suggested change
if ((RegNo < 2) || (RegNo > 3))
if (RegNo != 2 && RegNo != 3)

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Fixed

return MCDisassembler::Fail;

unsigned Reg = MR23DecoderTable[RegNo - 2];
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MCRegister

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Fixed

Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

const MCPhysReg SRDecoderTable[] = {
Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};

static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
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