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[CodeGen] commuteInstruction should update implicit-def #131361

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[CodeGen] commuteInstruction should update implicit-def #131361

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8d23eec
Precommit test
sdesmalen-arm Mar 10, 2025
d7abb47
[CodeGen] commuteInstruction should update implicit-def
sdesmalen-arm Mar 10, 2025
808ebbd
Use MachineInstr::substituteRegister
sdesmalen-arm Apr 2, 2025
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9 changes: 8 additions & 1 deletion llvm/lib/CodeGen/TargetInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,14 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
}

if (HasDef) {
CommutedMI->getOperand(0).setReg(Reg0);
// Use `substituteRegister` so that for a case like this:
// %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
// the implicit-def is also updated, to result in:
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
const TargetRegisterInfo &TRI =
*MI.getMF()->getSubtarget().getRegisterInfo();
Register FromReg = CommutedMI->getOperand(0).getReg();
CommutedMI->substituteRegister(FromReg, Reg0, /*SubRegIdx*/ 0, TRI);
CommutedMI->getOperand(0).setSubReg(SubReg0);
}
CommutedMI->getOperand(Idx2).setReg(Reg1);
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37 changes: 37 additions & 0 deletions llvm/test/CodeGen/X86/coalesce-commutative-implicit-def.mir
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@@ -0,0 +1,37 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=x86_64 -run-pass=register-coalescer -o - %s | FileCheck %s

# When the coalescer removes the COPY by commuting the operands of the AND, it should also update the `implicit-def` of the destination register.
---
name: implicit_def_dst
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: implicit_def_dst
; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]]
; CHECK-NEXT: RET 0, implicit [[MOV64rm]]
%0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
%1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
%1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit
%0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit
RET 0, implicit %0
...
# In case the MIR for some reason contains more than one implicit-def of the destination reg, then all should be updated.
---
name: two_implicit_defs_dst
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: two_implicit_defs_dst
; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]], implicit-def [[MOV64rm]]
; CHECK-NEXT: RET 0, implicit [[MOV64rm]]
%0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
%1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
%1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit, implicit-def %1:gr64_with_sub_8bit
%0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit
RET 0, implicit %0
...