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[RISCV] Add vector hasAndNot to enable optimizations #132438

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Merged
merged 3 commits into from
Mar 26, 2025
Merged

[RISCV] Add vector hasAndNot to enable optimizations #132438

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b52efb4
[RISCV] Add vector hasAndNot to enable optimizations
pfusik Mar 21, 2025
a25e006
[RISCV] Match VANDN ignoring XOR constant bits above SEW
topperc Mar 24, 2025
7eacdcf
[RISCV] VL pattern for VANDN ignoring XOR constant bits above SEW
pfusik Mar 25, 2025
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10 changes: 9 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -2052,14 +2052,22 @@ bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
EVT VT = Y.getValueType();

// FIXME: Support vectors once we have tests.
if (VT.isVector())
return false;

return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
(!isa<ConstantSDNode>(Y) || cast<ConstantSDNode>(Y)->isOpaque());
}

bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
EVT VT = Y.getValueType();

if (!VT.isVector())
return hasAndNotCompare(Y);

return Subtarget.hasStdExtZvkb();
}

bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
// Zbs provides BEXT[_I], which can be used with SEQZ/SNEZ as a bit test.
if (Subtarget.hasStdExtZbs())
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -535,6 +535,7 @@ class RISCVTargetLowering : public TargetLowering {
bool isCheapToSpeculateCtlz(Type *Ty) const override;
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
bool hasAndNotCompare(SDValue Y) const override;
bool hasAndNot(SDValue Y) const override;
bool hasBitTest(SDValue X, SDValue Y) const override;
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
Expand Down
11 changes: 7 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
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Expand Up @@ -603,13 +603,16 @@ multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name,
// This should match the logic in RISCVDAGToDAGISel::selectVSplat
def riscv_splat_vector : PatFrag<(ops node:$rs1),
(riscv_vmv_v_x_vl undef, node:$rs1, srcvalue)>;
def riscv_vnot : PatFrag<(ops node:$rs1), (xor node:$rs1,
(riscv_splat_vector -1))>;
def allonessew8 : ImmLeaf<XLenVT, "return SignExtend64<8>(Imm) == -1LL;">;
def allonessew16 : ImmLeaf<XLenVT, "return SignExtend64<16>(Imm) == -1LL;">;
def allonessew32 : ImmLeaf<XLenVT, "return SignExtend64<32>(Imm) == -1LL;">;
def allonessew64 : ImmLeaf<XLenVT, "return Imm == -1LL;">;

foreach vti = AllIntegerVectors in {
let Predicates = !listconcat([HasStdExtZvkb],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (and (riscv_vnot vti.RegClass:$rs1),
def : Pat<(vti.Vector (and (xor vti.RegClass:$rs1,
(riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW))),
vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
Expand Down Expand Up @@ -734,7 +737,7 @@ foreach vti = AllIntegerVectors in {
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (riscv_and_vl (riscv_xor_vl
(vti.Vector vti.RegClass:$rs1),
(riscv_splat_vector -1),
(riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW)),
(vti.Vector vti.RegClass:$passthru),
(vti.Mask VMV0:$vm),
VLOpFrag),
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21 changes: 9 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vandn.ll
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Expand Up @@ -16,9 +16,8 @@ define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:
; CHECK-ZVKB: # %bb.0:
; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 7
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
; CHECK-ZVKB-NEXT: ret
%cond = icmp sgt <8 x i8> %a, splat (i8 -1)
%r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer
Expand All @@ -37,9 +36,8 @@ define <4 x i16> @not_signbit_mask_v4i16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-ZVKB-LABEL: not_signbit_mask_v4i16:
; CHECK-ZVKB: # %bb.0:
; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 15
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
; CHECK-ZVKB-NEXT: ret
%cond = icmp sgt <4 x i16> %a, splat (i16 -1)
%r = select <4 x i1> %cond, <4 x i16> %b, <4 x i16> zeroinitializer
Expand All @@ -58,9 +56,8 @@ define <2 x i32> @not_signbit_mask_v2i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-ZVKB-LABEL: not_signbit_mask_v2i32:
; CHECK-ZVKB: # %bb.0:
; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 31
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
; CHECK-ZVKB-NEXT: ret
%cond = icmp sgt <2 x i32> %a, splat (i32 -1)
%r = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> zeroinitializer
Expand All @@ -78,10 +75,10 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
;
; CHECK-ZVKB-LABEL: not_signbit_mask_v2i64:
; CHECK-ZVKB: # %bb.0:
; CHECK-ZVKB-NEXT: li a0, 63
; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-ZVKB-NEXT: vsra.vx v8, v8, a0
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
; CHECK-ZVKB-NEXT: ret
%cond = icmp sgt <2 x i64> %a, splat (i64 -1)
%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
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Expand Up @@ -2580,9 +2580,8 @@ define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale
; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:
; CHECK-ZVKB: # %bb.0:
; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVKB-NEXT: vmsgt.vi v0, v8, -1
; CHECK-ZVKB-NEXT: vmv.v.i v8, 0
; CHECK-ZVKB-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 7
; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8
; CHECK-ZVKB-NEXT: ret
%cond = icmp sgt <vscale x 1 x i8> %a, splat (i8 -1)
%r = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %b, <vscale x 1 x i8> zeroinitializer
Expand Down