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[Target] Use *Set::insert_range (NFC) #132879

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3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -72,8 +72,7 @@ bool AArch64BranchTargets::runOnMachineFunction(MachineFunction &MF) {
SmallPtrSet<MachineBasicBlock *, 8> JumpTableTargets;
if (auto *JTI = MF.getJumpTableInfo())
for (auto &JTE : JTI->getJumpTables())
for (auto *MBB : JTE.MBBs)
JumpTableTargets.insert(MBB);
JumpTableTargets.insert_range(JTE.MBBs);

bool MadeChange = false;
bool HasWinCFI = MF.hasWinCFI();
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2412,8 +2412,7 @@ class AArch64Operand : public MCParsedAsmOperand {
else {
std::vector<unsigned> Regs = RegMap[std::make_pair(ElementWidth, Reg)];
assert(!Regs.empty() && "Invalid tile or element width!");
for (auto OutReg : Regs)
OutRegs.insert(OutReg);
OutRegs.insert_range(Regs);
}
}

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4 changes: 1 addition & 3 deletions llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1013,9 +1013,7 @@ int R600MachineCFGStructurizer::mergeLoop(MachineLoop *LoopRep) {
// We assume a single ExitBlk
MBBVector ExitBlks;
LoopRep->getExitBlocks(ExitBlks);
SmallPtrSet<MachineBasicBlock *, 2> ExitBlkSet;
for (MachineBasicBlock *MBB : ExitBlks)
ExitBlkSet.insert(MBB);
SmallPtrSet<MachineBasicBlock *, 2> ExitBlkSet(llvm::from_range, ExitBlks);
assert(ExitBlkSet.size() == 1);
MachineBasicBlock *ExitBlk = *ExitBlks.begin();
assert(ExitBlk && "Loop has several exit block");
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -120,8 +120,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// Collect all globals that had their storage promoted to a constant pool.
// Functions are emitted before variables, so this accumulates promoted
// globals from all functions in PromotedGlobals.
for (const auto *GV : AFI->getGlobalsPromotedToConstantPool())
PromotedGlobals.insert(GV);
PromotedGlobals.insert_range(AFI->getGlobalsPromotedToConstantPool());

// Calculate this function's optimization goal.
unsigned OptimizationGoal;
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMFrameLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3213,8 +3213,7 @@ void ARMFrameLowering::adjustForSegmentedStacks(
MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
PostStackMBB};

for (MachineBasicBlock *B : AddedBlocks)
BeforePrologueRegion.insert(B);
BeforePrologueRegion.insert_range(AddedBlocks);

for (const auto &LI : PrologueMBB.liveins()) {
for (MachineBasicBlock *PredBB : BeforePrologueRegion)
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5 changes: 2 additions & 3 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3139,9 +3139,8 @@ bool ARMTargetLowering::IsEligibleForTailCallOptimization(
// Sometimes, no register matches all of these conditions, so we can't do a
// tail-call.
if (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect) {
SmallSet<MCPhysReg, 5> AddressRegisters;
for (Register R : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
AddressRegisters.insert(R);
SmallSet<MCPhysReg, 5> AddressRegisters = {ARM::R0, ARM::R1, ARM::R2,
ARM::R3};
if (!(Subtarget->isThumb1Only() ||
MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true)))
AddressRegisters.insert(ARM::R12);
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -96,8 +96,7 @@ static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,

auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
for (unsigned Reg : Regs)
for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg))
UsesDefs.insert(Subreg);
UsesDefs.insert_range(TRI->subregs_inclusive(Reg));
};

InsertUsesDefs(LocalDefs, Defs);
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3 changes: 1 addition & 2 deletions llvm/lib/Target/Hexagon/BitTracker.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -965,8 +965,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
Targets.insert(&*Next);
}
} else {
for (const MachineBasicBlock *SB : B.successors())
Targets.insert(SB);
Targets.insert_range(B.successors());
}

for (const MachineBasicBlock *TB : Targets)
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3 changes: 1 addition & 2 deletions llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -779,8 +779,7 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
Targets.clear();
LLVM_DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG "
"successors\n");
for (const MachineBasicBlock *SB : B.successors())
Targets.insert(SB);
Targets.insert_range(B.successors());
}

for (const MachineBasicBlock *TB : Targets) {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -401,8 +401,7 @@ void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
continue;
if (B == Entry)
return false;
for (auto *P : B->predecessors())
Work.insert(P);
Work.insert_range(B->predecessors());
}
return true;
};
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4 changes: 1 addition & 3 deletions llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -801,9 +801,7 @@ bool HexagonLoadStoreWidening::replaceInsts(InstrGroup &OG, InstrGroup &NG) {
// the insertion point.

// Create a set of all instructions in OG (for quick lookup).
InstrSet OldMemInsts;
for (auto *I : OG)
OldMemInsts.insert(I);
InstrSet OldMemInsts(llvm::from_range, OG);

if (Mode == WideningMode::Load) {
// Find the first load instruction in the block that is present in OG.
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3 changes: 1 addition & 2 deletions llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2303,8 +2303,7 @@ bool HexagonLoopIdiomRecognize::processCopyingStore(Loop *CurLoop,
bool HexagonLoopIdiomRecognize::coverLoop(Loop *L,
SmallVectorImpl<Instruction*> &Insts) const {
SmallSet<BasicBlock*,8> LoopBlocks;
for (auto *B : L->blocks())
LoopBlocks.insert(B);
LoopBlocks.insert_range(L->blocks());

SetVector<Instruction*> Worklist(Insts.begin(), Insts.end());

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5 changes: 1 addition & 4 deletions llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -44,10 +44,7 @@ static cl::list<SPIRV::Capability::Capability>
// Use sets instead of cl::list to check "if contains" condition
struct AvoidCapabilitiesSet {
SmallSet<SPIRV::Capability::Capability, 4> S;
AvoidCapabilitiesSet() {
for (auto Cap : AvoidCapabilities)
S.insert(Cap);
}
AvoidCapabilitiesSet() { S.insert_range(AvoidCapabilities); }
};

char llvm::SPIRVModuleAnalysis::ID = 0;
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3 changes: 1 addition & 2 deletions llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1041,8 +1041,7 @@ X86SpeculativeLoadHardeningPass::tracePredStateThroughIndirectBranches(
IndirectTerminatedMBBs.insert(&MBB);

// Add all the successors to our target candidates.
for (MachineBasicBlock *Succ : MBB.successors())
IndirectTargetMBBs.insert(Succ);
IndirectTargetMBBs.insert_range(MBB.successors());
}

// Keep track of the cmov instructions we insert so we can return them.
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