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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV v16f32/v16i32 nodes if the upper elements are not demanded #134890

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Merged
merged 2 commits into from
Apr 9, 2025
Merged

[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV v16f32/v16i32 nodes if the upper elements are not demanded #134890

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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VP…
RKSimon Apr 8, 2025
b31012e
Merge branch 'main' into x86-demandelts-avx2-vpermv
RKSimon Apr 9, 2025
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4 changes: 3 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -43810,7 +43810,9 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
case X86ISD::VPERMV: {
SmallVector<int, 16> Mask;
SmallVector<SDValue, 2> Ops;
if ((VT.is256BitVector() || Subtarget.hasVLX()) &&
// We can always split v16i32/v16f32 AVX512 to v8i32/v8f32 AVX2 variants.
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Can we do it for v8i64/v8f64?

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Unfortunately not - avx2 vpermq takes an immediate (X86ISD::VPERMI) - we already handle 512->ymm X86ISD::VPERMI though

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Ok, it's quite queer.

if ((VT.is256BitVector() || Subtarget.hasVLX() || VT == MVT::v16i32 ||
VT == MVT::v16f32) &&
getTargetShuffleMask(Op, /*AllowSentinelZero=*/false, Ops, Mask)) {
// For lane-crossing shuffles, only split in half in case we're still
// referencing higher elements.
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
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Expand Up @@ -491,8 +491,8 @@ define <4 x float> @test_v16f32_0_1_3_6 (<16 x float> %v) {
; ALL-LABEL: test_v16f32_0_1_3_6:
; ALL: # %bb.0:
; ALL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,1,3,6]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; ALL-NEXT: vzeroupper
; ALL-NEXT: retq
%res = shufflevector <16 x float> %v, <16 x float> poison, <4 x i32> <i32 0, i32 1, i32 3, i32 6>
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