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[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector #135010

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Merged
merged 8 commits into from
May 6, 2025
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[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector #135010

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e5c1914
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast …
Apr 9, 2025
483c273
Fix for test cases failure
Apr 16, 2025
a48660c
Merge branch 'llvm:main' into ZextBuildVec
rohitaggarwal007 Apr 25, 2025
ff669c6
Fix for the test case failure
Apr 25, 2025
e776464
Merge branch 'llvm:main' into ZextBuildVec
rohitaggarwal007 Apr 29, 2025
9dc5117
Fix the bad codegen
May 5, 2025
dd28865
Revert back two testcases formatting
May 6, 2025
321b52e
Move folding logic from DAGCombiner to X86ISelLowering as it is speci…
May 6, 2025
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63 changes: 63 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -14195,6 +14195,66 @@ static SDValue widenAbs(SDNode *Extend, SelectionDAG &DAG) {
return DAG.getZExtOrTrunc(NewAbs, SDLoc(Extend), VT);
}

// Try to widen the build vector and bitcast it to the type of zext.
// This is a special case for the 128-bit vector types. Intention is to remove
// the zext and replace it with a bitcast the wider type. While lowering
// the bitcast is removed and extra commutation due to zext is avoided.
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DAG format comment of the matched pattern

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@arsenm Add such comment like zext(build_vec) -> bitcast(build_vec). which visualize the transformation, right?

static SDValue widenBuildVec(SDNode *Extend, SelectionDAG &DAG) {

assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend.");

EVT ExtendVT = Extend->getValueType(0);

SDValue BV = Extend->getOperand(0);
if (BV.getOpcode() != ISD::BUILD_VECTOR || !BV.hasOneUse())
return SDValue();

SDLoc dl(BV);
EVT VT = BV.getValueType();
EVT EltVT = BV.getOperand(0).getValueType();
unsigned NumElts = VT.getVectorNumElements();

const TargetLowering &TLI = DAG.getTargetLoweringInfo();

if (TLI.getTypeAction(*DAG.getContext(), VT) !=
TargetLowering::TypeWidenVector)
return SDValue();

EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();

SmallVector<SDValue, 16> NewOps(BV->op_begin(), BV->op_end());
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
// Fill the new elements with Zero.
NewOps.append(WidenNumElts - NumElts, DAG.getConstant(0, dl, EltVT));
// Compute the step to place the elements in the right place and control the
// iteration.
unsigned step = WidenNumElts / NumElts;
if (WidenVT.is128BitVector()) {
if (step > 1 && Extend->getValueSizeInBits(0) == WidenVT.getSizeInBits()) {
for (int i = NumElts - 1, j = WidenNumElts - step; i > 0;
i--, j -= step) {
SDValue temp = NewOps[i];
NewOps[i] = NewOps[j];
NewOps[j] = temp;
}
// Create new build vector with WidenVT and NewOps
SDValue NewBV = DAG.getBuildVector(WidenVT, dl, NewOps);
// Replace the old build vector with the new one. Bitcast the
// new build vector to the type of the zext.
SDValue NewBVBitcast = DAG.getBitcast(ExtendVT, NewBV);
DAG.ReplaceAllUsesOfValueWith(SDValue(Extend, 0), NewBVBitcast);
LLVM_DEBUG(
dbgs() << DAG.getMachineFunction().getFunction().getName()
<< " - Widening buildvector and replace zext with bitcast\n";
BV.dump(); Extend->dump(); dbgs() << " to \n";
NewBV.getNode()->dump(); NewBVBitcast->dump(););
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I would remove this whole debug print. You should see the transform triggered in the generic dag combine case. You aslo don't need all of the manual dumping, you can directly use operator<<

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Sure, I will fix it

return NewBV;
}
}
return SDValue();
}

SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
Expand Down Expand Up @@ -14521,6 +14581,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
return SDValue(CSENode, 0);
}

if (SDValue V = widenBuildVec(N, DAG))
return V;

return SDValue();
}

Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/PowerPC/custom-stov.ll
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Expand Up @@ -15,18 +15,18 @@ define void @_blah() {
; CHECK-NEXT: vperm v2, v4, v3, v2
; CHECK-NEXT: lwz r4, 16(0)
; CHECK-NEXT: stvx v2, 0, r5
; CHECK-NEXT: lhz r5, -64(r1)
; CHECK-NEXT: lhz r6, -58(r1)
; CHECK-NEXT: lhz r7, -52(r1)
; CHECK-NEXT: sth r4, -34(r1)
; CHECK-NEXT: sth r3, -36(r1)
; CHECK-NEXT: sth r3, -34(r1)
; CHECK-NEXT: sth r3, -38(r1)
; CHECK-NEXT: sth r3, -42(r1)
; CHECK-NEXT: sth r3, -46(r1)
; CHECK-NEXT: lhz r3, -52(r1)
; CHECK-NEXT: sth r3, -40(r1)
; CHECK-NEXT: lhz r3, -58(r1)
; CHECK-NEXT: sth r3, -44(r1)
; CHECK-NEXT: lhz r3, -64(r1)
; CHECK-NEXT: sth r4, -36(r1)
; CHECK-NEXT: sth r3, -48(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: sth r7, -38(r1)
; CHECK-NEXT: sth r6, -42(r1)
; CHECK-NEXT: sth r5, -46(r1)
; CHECK-NEXT: lvx v2, 0, r3
; CHECK-NEXT: addi r3, r1, -32
; CHECK-NEXT: vsldoi v3, v2, v2, 8
Expand Down
104 changes: 57 additions & 47 deletions llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
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Expand Up @@ -327,9 +327,9 @@ define void @test16(ptr nocapture readonly %sums, i32 signext %delta, i32 signex
; P9BE-AIX32-NEXT: sth 3, -32(1)
; P9BE-AIX32-NEXT: lwz 3, L..C3(2) # %const.0
; P9BE-AIX32-NEXT: lxv 3, -32(1)
; P9BE-AIX32-NEXT: vmrghh 4, 2, 4
; P9BE-AIX32-NEXT: vmrghh 4, 4, 2
; P9BE-AIX32-NEXT: lxv 0, 0(3)
; P9BE-AIX32-NEXT: vmrghh 3, 2, 3
; P9BE-AIX32-NEXT: vmrghh 3, 3, 2
; P9BE-AIX32-NEXT: vsplth 2, 2, 0
; P9BE-AIX32-NEXT: xxmrghw 2, 2, 4
; P9BE-AIX32-NEXT: xxperm 3, 2, 0
Expand Down Expand Up @@ -403,25 +403,29 @@ define void @test8(ptr nocapture readonly %sums, i32 signext %delta, i32 signext
; P9BE-LABEL: test8:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: add 6, 3, 4
; P9BE-NEXT: li 7, 8
; P9BE-NEXT: lxsibzx 3, 3, 4
; P9BE-NEXT: lxsibzx 2, 3, 4
; P9BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; P9BE-NEXT: addi 3, 3, .LCPI3_0@toc@l
; P9BE-NEXT: lxv 0, 0(3)
; P9BE-NEXT: li 3, 0
; P9BE-NEXT: mtvsrwz 3, 3
; P9BE-NEXT: li 3, 8
; P9BE-NEXT: vspltb 4, 3, 7
; P9BE-NEXT: xxperm 2, 3, 0
; P9BE-NEXT: lxsibzx 0, 6, 3
; P9BE-NEXT: addis 3, 2, .LCPI3_1@toc@ha
; P9BE-NEXT: lxsibzx 0, 6, 7
; P9BE-NEXT: addis 6, 2, .LCPI3_0@toc@ha
; P9BE-NEXT: addi 3, 3, .LCPI3_1@toc@l
; P9BE-NEXT: addi 6, 6, .LCPI3_0@toc@l
; P9BE-NEXT: lxv 1, 0(6)
; P9BE-NEXT: li 6, 0
; P9BE-NEXT: mtvsrwz 2, 6
; P9BE-NEXT: xxperm 0, 2, 1
; P9BE-NEXT: xxperm 3, 2, 1
; P9BE-NEXT: vspltb 2, 2, 7
; P9BE-NEXT: vmrghh 3, 3, 2
; P9BE-NEXT: xxspltw 1, 2, 0
; P9BE-NEXT: xxmrghw 3, 3, 0
; P9BE-NEXT: vmrghh 2, 4, 2
; P9BE-NEXT: lxv 1, 0(3)
; P9BE-NEXT: addis 3, 2, .LCPI3_2@toc@ha
; P9BE-NEXT: addi 3, 3, .LCPI3_2@toc@l
; P9BE-NEXT: xxmrghw 2, 4, 2
; P9BE-NEXT: xxperm 3, 0, 1
; P9BE-NEXT: lxv 0, 0(3)
; P9BE-NEXT: li 3, 0
; P9BE-NEXT: xxperm 3, 1, 0
; P9BE-NEXT: vmrghh 3, 4, 3
; P9BE-NEXT: xxmrghw 3, 3, 4
; P9BE-NEXT: xxperm 3, 2, 0
; P9BE-NEXT: xxspltw 2, 3, 1
; P9BE-NEXT: vadduwm 2, 3, 2
; P9BE-NEXT: vextuwlx 3, 3, 2
Expand All @@ -432,23 +436,26 @@ define void @test8(ptr nocapture readonly %sums, i32 signext %delta, i32 signext
; P9BE-AIX-LABEL: test8:
; P9BE-AIX: # %bb.0: # %entry
; P9BE-AIX-NEXT: add 6, 3, 4
; P9BE-AIX-NEXT: li 7, 8
; P9BE-AIX-NEXT: lxsibzx 3, 3, 4
; P9BE-AIX-NEXT: ld 3, L..C5(2) # %const.1
; P9BE-AIX-NEXT: lxsibzx 0, 6, 7
; P9BE-AIX-NEXT: ld 6, L..C6(2) # %const.0
; P9BE-AIX-NEXT: lxv 1, 0(6)
; P9BE-AIX-NEXT: li 6, 0
; P9BE-AIX-NEXT: mtvsrwz 2, 6
; P9BE-AIX-NEXT: xxperm 0, 2, 1
; P9BE-AIX-NEXT: xxperm 3, 2, 1
; P9BE-AIX-NEXT: vspltb 2, 2, 7
; P9BE-AIX-NEXT: vmrghh 3, 3, 2
; P9BE-AIX-NEXT: xxspltw 1, 2, 0
; P9BE-AIX-NEXT: xxmrghw 3, 3, 0
; P9BE-AIX-NEXT: lxsibzx 2, 3, 4
; P9BE-AIX-NEXT: ld 3, L..C5(2) # %const.0
; P9BE-AIX-NEXT: lxv 0, 0(3)
; P9BE-AIX-NEXT: li 3, 0
; P9BE-AIX-NEXT: mtvsrwz 3, 3
; P9BE-AIX-NEXT: li 3, 8
; P9BE-AIX-NEXT: vspltb 4, 3, 7
; P9BE-AIX-NEXT: xxperm 2, 3, 0
; P9BE-AIX-NEXT: lxsibzx 0, 6, 3
; P9BE-AIX-NEXT: ld 3, L..C6(2) # %const.1
; P9BE-AIX-NEXT: vmrghh 2, 4, 2
; P9BE-AIX-NEXT: lxv 1, 0(3)
; P9BE-AIX-NEXT: ld 3, L..C7(2) # %const.2
; P9BE-AIX-NEXT: xxmrghw 2, 4, 2
; P9BE-AIX-NEXT: xxperm 3, 0, 1
; P9BE-AIX-NEXT: lxv 0, 0(3)
; P9BE-AIX-NEXT: li 3, 0
; P9BE-AIX-NEXT: xxperm 3, 1, 0
; P9BE-AIX-NEXT: vmrghh 3, 4, 3
; P9BE-AIX-NEXT: xxmrghw 3, 3, 4
; P9BE-AIX-NEXT: xxperm 3, 2, 0
; P9BE-AIX-NEXT: xxspltw 2, 3, 1
; P9BE-AIX-NEXT: vadduwm 2, 3, 2
; P9BE-AIX-NEXT: vextuwlx 3, 3, 2
Expand All @@ -459,22 +466,25 @@ define void @test8(ptr nocapture readonly %sums, i32 signext %delta, i32 signext
; P9BE-AIX32-LABEL: test8:
; P9BE-AIX32: # %bb.0: # %entry
; P9BE-AIX32-NEXT: add 6, 3, 4
; P9BE-AIX32-NEXT: li 7, 8
; P9BE-AIX32-NEXT: lxsibzx 3, 3, 4
; P9BE-AIX32-NEXT: lwz 3, L..C4(2) # %const.1
; P9BE-AIX32-NEXT: lxsibzx 0, 6, 7
; P9BE-AIX32-NEXT: lwz 6, L..C5(2) # %const.0
; P9BE-AIX32-NEXT: lxv 1, 0(6)
; P9BE-AIX32-NEXT: li 6, 0
; P9BE-AIX32-NEXT: mtvsrwz 2, 6
; P9BE-AIX32-NEXT: xxperm 0, 2, 1
; P9BE-AIX32-NEXT: xxperm 3, 2, 1
; P9BE-AIX32-NEXT: vspltb 2, 2, 7
; P9BE-AIX32-NEXT: vmrghh 3, 3, 2
; P9BE-AIX32-NEXT: xxspltw 1, 2, 0
; P9BE-AIX32-NEXT: xxmrghw 3, 3, 0
; P9BE-AIX32-NEXT: lxsibzx 2, 3, 4
; P9BE-AIX32-NEXT: lwz 3, L..C4(2) # %const.0
; P9BE-AIX32-NEXT: lxv 0, 0(3)
; P9BE-AIX32-NEXT: xxperm 3, 1, 0
; P9BE-AIX32-NEXT: li 3, 0
; P9BE-AIX32-NEXT: mtvsrwz 3, 3
; P9BE-AIX32-NEXT: li 3, 8
; P9BE-AIX32-NEXT: vspltb 4, 3, 7
; P9BE-AIX32-NEXT: xxperm 2, 3, 0
; P9BE-AIX32-NEXT: lxsibzx 0, 6, 3
; P9BE-AIX32-NEXT: lwz 3, L..C5(2) # %const.1
; P9BE-AIX32-NEXT: vmrghh 2, 4, 2
; P9BE-AIX32-NEXT: lxv 1, 0(3)
; P9BE-AIX32-NEXT: lwz 3, L..C6(2) # %const.2
; P9BE-AIX32-NEXT: xxmrghw 2, 4, 2
; P9BE-AIX32-NEXT: xxperm 3, 0, 1
; P9BE-AIX32-NEXT: lxv 0, 0(3)
; P9BE-AIX32-NEXT: vmrghh 3, 4, 3
; P9BE-AIX32-NEXT: xxmrghw 3, 3, 4
; P9BE-AIX32-NEXT: xxperm 3, 2, 0
; P9BE-AIX32-NEXT: xxspltw 2, 3, 1
; P9BE-AIX32-NEXT: vadduwm 2, 3, 2
; P9BE-AIX32-NEXT: stxv 2, -16(1)
Expand Down
30 changes: 24 additions & 6 deletions llvm/test/CodeGen/SystemZ/vec-mul-07.ll
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Expand Up @@ -7,7 +7,11 @@
define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmleb %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI0_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmlhw %v24, %v1, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand All @@ -21,7 +25,12 @@ define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2) {
define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlob %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmlhw %v24, %v2, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand Down Expand Up @@ -63,7 +72,11 @@ define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2) {
define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmleh %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI4_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmlf %v24, %v1, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand All @@ -77,7 +90,12 @@ define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2) {
define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmloh %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI5_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmlf %v24, %v2, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand Down Expand Up @@ -119,7 +137,7 @@ define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2) {
define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlef %v24, %v24, %v26
; CHECK-NEXT: vgbm %v24, 0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand All @@ -133,7 +151,7 @@ define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2) {
define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlof %v24, %v24, %v26
; CHECK-NEXT: vgbm %v24, 0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand Down
30 changes: 24 additions & 6 deletions llvm/test/CodeGen/SystemZ/vec-mul-09.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,11 @@
define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaleb %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI0_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmalhw %v24, %v1, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand All @@ -22,7 +26,12 @@ define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalob %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmalhw %v24, %v2, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand Down Expand Up @@ -67,7 +76,11 @@ define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaleh %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI4_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmalf %v24, %v1, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand All @@ -82,7 +95,12 @@ define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaloh %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI5_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmalf %v24, %v2, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand Down Expand Up @@ -127,7 +145,7 @@ define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalef %v24, %v24, %v26, %v28
; CHECK-NEXT: vlr %v24, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand All @@ -142,7 +160,7 @@ define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalof %v24, %v24, %v26, %v28
; CHECK-NEXT: vlr %v24, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand Down
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