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[SPARC] Use lzcnt to implement CTLZ when we have VIS3 #135715

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Merged
merged 12 commits into from
Apr 17, 2025
Merged

[SPARC] Use lzcnt to implement CTLZ when we have VIS3 #135715

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70b5a4f
[𝘀𝗽𝗿] changes to main this commit is based on
koachan Apr 15, 2025
5ad296c
[𝘀𝗽𝗿] initial version
koachan Apr 15, 2025
5e8bff2
[𝘀𝗽𝗿] changes introduced through rebase
koachan Apr 15, 2025
8e944dd
Update tests
koachan Apr 15, 2025
a4deacf
[𝘀𝗽𝗿] changes introduced through rebase
koachan Apr 16, 2025
545a55c
Use Promote for i32 lzcnt
koachan Apr 16, 2025
af07168
[𝘀𝗽𝗿] changes introduced through rebase
YonahGoldberg Apr 16, 2025
49e0e47
Rebase & update
koachan Apr 16, 2025
6e86581
Promote i32 CTLZ when we don't have VIS3 or POPC
koachan Apr 17, 2025
c196033
Add back i32 pattern since the instruction is also usable in 32-bit mode
koachan Apr 17, 2025
df2770a
Adjust codegen parameters
koachan Apr 17, 2025
5502caf
Adjust tests
koachan Apr 17, 2025
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12 changes: 10 additions & 2 deletions llvm/lib/Target/Sparc/SparcISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
Expand Down Expand Up @@ -1753,7 +1754,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTPOP, MVT::i64,
Subtarget->usePopc() ? Legal : Expand);
setOperationAction(ISD::CTTZ , MVT::i64, Expand);
setOperationAction(ISD::CTLZ , MVT::i64, Expand);
setOperationAction(ISD::CTLZ, MVT::i64,
Subtarget->isVIS3() ? Legal : LibCall);
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
setOperationAction(ISD::ROTL , MVT::i64, Expand);
setOperationAction(ISD::ROTR , MVT::i64, Expand);
Expand Down Expand Up @@ -1815,7 +1817,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FMA , MVT::f32, Expand);
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i32,
Subtarget->isVIS3() ? Promote : LibCall);
setOperationAction(ISD::ROTL , MVT::i32, Expand);
setOperationAction(ISD::ROTR , MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Expand Down Expand Up @@ -1986,6 +1989,11 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
if (Subtarget->hasLeonCycleCounter())
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);

if (Subtarget->isVIS3()) {
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
}

setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

setMinFunctionAlignment(Align(4));
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/Sparc/SparcInstrVIS.td
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Original file line number Diff line number Diff line change
Expand Up @@ -294,4 +294,7 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
// VIS3 instruction patterns.
let Predicates = [HasVIS3] in {
def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;

def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
def : Pat<(i64 (ctlz_zero_undef i64:$src)), (LZCNT $src)>;
} // Predicates = [HasVIS3]
313 changes: 313 additions & 0 deletions llvm/test/CodeGen/SPARC/ctlz.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,313 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9
; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC
; RUN: llc < %s -mtriple=sparcv9 -mattr=vis3 | FileCheck %s -check-prefix=VIS3

define i32 @i32_nopoison(i32 %x) nounwind {
; V9-LABEL: i32_nopoison:
; V9: ! %bb.0:
; V9-NEXT: cmp %o0, 0
; V9-NEXT: be %icc, .LBB0_2
; V9-NEXT: nop
; V9-NEXT: ! %bb.1: ! %cond.false
; V9-NEXT: srl %o0, 1, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 2, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 4, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 8, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 16, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: xor %o0, -1, %o0
; V9-NEXT: srl %o0, 1, %o1
; V9-NEXT: sethi 1398101, %o2
; V9-NEXT: or %o2, 341, %o2
; V9-NEXT: and %o1, %o2, %o1
; V9-NEXT: sub %o0, %o1, %o0
; V9-NEXT: sethi 838860, %o1
; V9-NEXT: or %o1, 819, %o1
; V9-NEXT: and %o0, %o1, %o2
; V9-NEXT: srl %o0, 2, %o0
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: add %o2, %o0, %o0
; V9-NEXT: srl %o0, 4, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sethi 246723, %o1
; V9-NEXT: or %o1, 783, %o1
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: sll %o0, 8, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sll %o0, 16, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: retl
; V9-NEXT: srl %o0, 24, %o0
; V9-NEXT: .LBB0_2:
; V9-NEXT: retl
; V9-NEXT: mov 32, %o0
;
; POPC-LABEL: i32_nopoison:
; POPC: ! %bb.0:
; POPC-NEXT: cmp %o0, 0
; POPC-NEXT: be %icc, .LBB0_2
; POPC-NEXT: nop
; POPC-NEXT: ! %bb.1: ! %cond.false
; POPC-NEXT: srl %o0, 1, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 2, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 4, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 8, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 16, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: xor %o0, -1, %o0
; POPC-NEXT: srl %o0, 0, %o0
; POPC-NEXT: retl
; POPC-NEXT: popc %o0, %o0
; POPC-NEXT: .LBB0_2:
; POPC-NEXT: retl
; POPC-NEXT: mov 32, %o0
;
; VIS3-LABEL: i32_nopoison:
; VIS3: ! %bb.0:
; VIS3-NEXT: cmp %o0, 0
; VIS3-NEXT: be %icc, .LBB0_2
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The branch is redundant, but I guess there is nothing we can do with it right now. It must've been created too early.

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Those turns out to be controlled by the codegen parameters you mentioned above, it seems.

; VIS3-NEXT: nop
; VIS3-NEXT: ! %bb.1: ! %cond.false
; VIS3-NEXT: sllx %o0, 32, %o0
; VIS3-NEXT: retl
; VIS3-NEXT: lzcnt %o0, %o0
; VIS3-NEXT: .LBB0_2:
; VIS3-NEXT: retl
; VIS3-NEXT: mov 32, %o0
%ret = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
ret i32 %ret
}

define i32 @i32_poison(i32 %x) nounwind {
; V9-LABEL: i32_poison:
; V9: ! %bb.0:
; V9-NEXT: srl %o0, 1, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 2, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 4, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 8, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srl %o0, 16, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: xor %o0, -1, %o0
; V9-NEXT: srl %o0, 1, %o1
; V9-NEXT: sethi 1398101, %o2
; V9-NEXT: or %o2, 341, %o2
; V9-NEXT: and %o1, %o2, %o1
; V9-NEXT: sub %o0, %o1, %o0
; V9-NEXT: sethi 838860, %o1
; V9-NEXT: or %o1, 819, %o1
; V9-NEXT: and %o0, %o1, %o2
; V9-NEXT: srl %o0, 2, %o0
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: add %o2, %o0, %o0
; V9-NEXT: srl %o0, 4, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sethi 246723, %o1
; V9-NEXT: or %o1, 783, %o1
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: sll %o0, 8, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sll %o0, 16, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: retl
; V9-NEXT: srl %o0, 24, %o0
;
; POPC-LABEL: i32_poison:
; POPC: ! %bb.0:
; POPC-NEXT: srl %o0, 1, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 2, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 4, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 8, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srl %o0, 16, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: xor %o0, -1, %o0
; POPC-NEXT: srl %o0, 0, %o0
; POPC-NEXT: retl
; POPC-NEXT: popc %o0, %o0
;
; VIS3-LABEL: i32_poison:
; VIS3: ! %bb.0:
; VIS3-NEXT: sllx %o0, 32, %o0
; VIS3-NEXT: retl
; VIS3-NEXT: lzcnt %o0, %o0
%ret = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
ret i32 %ret
}

define i64 @i64_nopoison(i64 %x) nounwind {
; V9-LABEL: i64_nopoison:
; V9: ! %bb.0:
; V9-NEXT: brz %o0, .LBB2_2
; V9-NEXT: nop
; V9-NEXT: ! %bb.1: ! %cond.false
; V9-NEXT: srlx %o0, 1, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 2, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 4, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 8, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 16, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 32, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: xor %o0, -1, %o0
; V9-NEXT: srlx %o0, 1, %o1
; V9-NEXT: sethi 1398101, %o2
; V9-NEXT: or %o2, 341, %o2
; V9-NEXT: sllx %o2, 32, %o3
; V9-NEXT: or %o3, %o2, %o2
; V9-NEXT: and %o1, %o2, %o1
; V9-NEXT: sub %o0, %o1, %o0
; V9-NEXT: sethi 838860, %o1
; V9-NEXT: or %o1, 819, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: and %o0, %o1, %o2
; V9-NEXT: srlx %o0, 2, %o0
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: add %o2, %o0, %o0
; V9-NEXT: srlx %o0, 4, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sethi 246723, %o1
; V9-NEXT: or %o1, 783, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: sethi 16448, %o1
; V9-NEXT: or %o1, 257, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: mulx %o0, %o1, %o0
; V9-NEXT: retl
; V9-NEXT: srlx %o0, 56, %o0
; V9-NEXT: .LBB2_2:
; V9-NEXT: retl
; V9-NEXT: mov 64, %o0
;
; POPC-LABEL: i64_nopoison:
; POPC: ! %bb.0:
; POPC-NEXT: brz %o0, .LBB2_2
; POPC-NEXT: nop
; POPC-NEXT: ! %bb.1: ! %cond.false
; POPC-NEXT: srlx %o0, 1, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 2, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 4, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 8, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 16, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 32, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: xor %o0, -1, %o0
; POPC-NEXT: retl
; POPC-NEXT: popc %o0, %o0
; POPC-NEXT: .LBB2_2:
; POPC-NEXT: retl
; POPC-NEXT: mov 64, %o0
;
; VIS3-LABEL: i64_nopoison:
; VIS3: ! %bb.0:
; VIS3-NEXT: brz %o0, .LBB2_2
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This is odd, I'd expect no branches here.

; VIS3-NEXT: nop
; VIS3-NEXT: ! %bb.1: ! %cond.false
; VIS3-NEXT: retl
; VIS3-NEXT: lzcnt %o0, %o0
; VIS3-NEXT: .LBB2_2:
; VIS3-NEXT: retl
; VIS3-NEXT: mov 64, %o0
%ret = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
ret i64 %ret
}

define i64 @i64_poison(i64 %x) nounwind {
; V9-LABEL: i64_poison:
; V9: ! %bb.0:
; V9-NEXT: srlx %o0, 1, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 2, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 4, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 8, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 16, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: srlx %o0, 32, %o1
; V9-NEXT: or %o0, %o1, %o0
; V9-NEXT: xor %o0, -1, %o0
; V9-NEXT: srlx %o0, 1, %o1
; V9-NEXT: sethi 1398101, %o2
; V9-NEXT: or %o2, 341, %o2
; V9-NEXT: sllx %o2, 32, %o3
; V9-NEXT: or %o3, %o2, %o2
; V9-NEXT: and %o1, %o2, %o1
; V9-NEXT: sub %o0, %o1, %o0
; V9-NEXT: sethi 838860, %o1
; V9-NEXT: or %o1, 819, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: and %o0, %o1, %o2
; V9-NEXT: srlx %o0, 2, %o0
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: add %o2, %o0, %o0
; V9-NEXT: srlx %o0, 4, %o1
; V9-NEXT: add %o0, %o1, %o0
; V9-NEXT: sethi 246723, %o1
; V9-NEXT: or %o1, 783, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: and %o0, %o1, %o0
; V9-NEXT: sethi 16448, %o1
; V9-NEXT: or %o1, 257, %o1
; V9-NEXT: sllx %o1, 32, %o2
; V9-NEXT: or %o2, %o1, %o1
; V9-NEXT: mulx %o0, %o1, %o0
; V9-NEXT: retl
; V9-NEXT: srlx %o0, 56, %o0
;
; POPC-LABEL: i64_poison:
; POPC: ! %bb.0:
; POPC-NEXT: srlx %o0, 1, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 2, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 4, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 8, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 16, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: srlx %o0, 32, %o1
; POPC-NEXT: or %o0, %o1, %o0
; POPC-NEXT: xor %o0, -1, %o0
; POPC-NEXT: retl
; POPC-NEXT: popc %o0, %o0
;
; VIS3-LABEL: i64_poison:
; VIS3: ! %bb.0:
; VIS3-NEXT: retl
; VIS3-NEXT: lzcnt %o0, %o0
%ret = call i64 @llvm.ctlz.i64(i64 %x, i1 true)
ret i64 %ret
}
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