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[XCore] TableGen-erate SDNode descriptions #138869

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May 7, 2025
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1 change: 1 addition & 0 deletions llvm/lib/Target/XCore/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM XCoreGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)

add_public_tablegen_target(XCoreCommonTableGen)
Expand Down
27 changes: 0 additions & 27 deletions llvm/lib/Target/XCore/XCoreISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -40,33 +40,6 @@ using namespace llvm;

#define DEBUG_TYPE "xcore-lower"

const char *XCoreTargetLowering::
getTargetNodeName(unsigned Opcode) const
{
switch ((XCoreISD::NodeType)Opcode)
{
case XCoreISD::FIRST_NUMBER : break;
case XCoreISD::BL : return "XCoreISD::BL";
case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
case XCoreISD::STWSP : return "XCoreISD::STWSP";
case XCoreISD::RETSP : return "XCoreISD::RETSP";
case XCoreISD::LADD : return "XCoreISD::LADD";
case XCoreISD::LSUB : return "XCoreISD::LSUB";
case XCoreISD::LMUL : return "XCoreISD::LMUL";
case XCoreISD::MACCU : return "XCoreISD::MACCU";
case XCoreISD::MACCS : return "XCoreISD::MACCS";
case XCoreISD::CRC8 : return "XCoreISD::CRC8";
case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
}
return nullptr;
}

XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
: TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
Expand Down
63 changes: 0 additions & 63 deletions llvm/lib/Target/XCore/XCoreISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,65 +23,6 @@ namespace llvm {
// Forward delcarations
class XCoreSubtarget;

namespace XCoreISD {
enum NodeType : unsigned {
// Start the numbering where the builtin ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END,

// Branch and link (call)
BL,

// pc relative address
PCRelativeWrapper,

// dp relative address
DPRelativeWrapper,

// cp relative address
CPRelativeWrapper,

// Load word from stack
LDWSP,

// Store word to stack
STWSP,

// Corresponds to retsp instruction
RETSP,

// Corresponds to LADD instruction
LADD,

// Corresponds to LSUB instruction
LSUB,

// Corresponds to LMUL instruction
LMUL,

// Corresponds to MACCU instruction
MACCU,

// Corresponds to MACCS instruction
MACCS,

// Corresponds to CRC8 instruction
CRC8,

// Jumptable branch.
BR_JT,

// Jumptable branch using long branches for each entry.
BR_JT32,

// Offset from frame pointer to the first (possible) on-stack argument
FRAME_TO_ARGS_OFFSET,

// Exception handler return. The stack is restored to the first
// followed by a jump to the second argument.
EH_RETURN,
};
}

//===--------------------------------------------------------------------===//
// TargetLowering Implementation
//===--------------------------------------------------------------------===//
Expand Down Expand Up @@ -109,10 +50,6 @@ namespace llvm {
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const override;

/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
const char *getTargetNodeName(unsigned Opcode) const override;

MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,19 @@
//
//===----------------------------------------------------------------------===//

#include "XCoreSelectionDAGInfo.h"
#include "XCoreTargetMachine.h"

#define GET_SDNODE_DESC
#include "XCoreGenSDNodeInfo.inc"

using namespace llvm;

#define DEBUG_TYPE "xcore-selectiondag-info"

XCoreSelectionDAGInfo::XCoreSelectionDAGInfo()
: SelectionDAGGenTargetInfo(XCoreGenSDNodeInfo) {}

SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
Expand Down
9 changes: 7 additions & 2 deletions llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,15 @@

#include "llvm/CodeGen/SelectionDAGTargetInfo.h"

#define GET_SDNODE_ENUM
#include "XCoreGenSDNodeInfo.inc"

namespace llvm {

class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo {
class XCoreSelectionDAGInfo : public SelectionDAGGenTargetInfo {
public:
XCoreSelectionDAGInfo();

SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1, SDValue Op2,
SDValue Op3, Align Alignment, bool isVolatile,
Expand All @@ -27,6 +32,6 @@ class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo {
MachinePointerInfo SrcPtrInfo) const override;
};

}
} // namespace llvm

#endif