[AMDGPU][NFC] Get rid of OPW constants. #139074
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We can infer the widths from register classes and represent them as numbers.
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@llvm/pr-subscribers-backend-amdgpu Author: Ivan Kosarev (kosarev) ChangesWe can infer the widths from register classes and represent them as numbers. Patch is 40.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/139074.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 486c1defc332a..d2f18fefd9866 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -161,13 +161,11 @@ static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr,
const MCDisassembler *Decoder) { \
assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
- return addOperand(Inst, \
- DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm)); \
+ return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm)); \
}
static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
- AMDGPUDisassembler::OpWidthTy OpWidth,
- unsigned Imm, unsigned EncImm,
+ unsigned OpWidth, unsigned Imm, unsigned EncImm,
const MCDisassembler *Decoder) {
assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
@@ -186,7 +184,7 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
// Used by AV_ register classes (AGPR or VGPR only register operands).
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
@@ -194,7 +192,7 @@ static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
}
// Decoder for Src(9-bit encoding) registers only.
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
@@ -204,7 +202,7 @@ static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
// Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set
// Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
// only.
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
@@ -212,7 +210,7 @@ static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
// Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
// Imm{9} is acc, registers only.
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
@@ -224,7 +222,7 @@ static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
// will be decoded and InstPrinter will report warning. Immediate will be
// decoded into constant matching the OperandType (important for floating point
// types).
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
@@ -233,14 +231,14 @@ static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
// Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
// and decode using 'enum10' from decodeSrcOp.
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
}
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
@@ -265,21 +263,21 @@ DECODE_OPERAND_REG_8(VReg_384)
DECODE_OPERAND_REG_8(VReg_512)
DECODE_OPERAND_REG_8(VReg_1024)
-DECODE_OPERAND_SREG_7(SReg_32, OPW32)
-DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
-DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
-DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
-DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
-DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
-DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
-DECODE_OPERAND_SREG_7(SReg_96, OPW96)
-DECODE_OPERAND_SREG_7(SReg_128, OPW128)
-DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
-DECODE_OPERAND_SREG_7(SReg_256, OPW256)
-DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
-DECODE_OPERAND_SREG_7(SReg_512, OPW512)
-
-DECODE_OPERAND_SREG_8(SReg_64, OPW64)
+DECODE_OPERAND_SREG_7(SReg_32, 32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0, 32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC, 32)
+DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, 32)
+DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, 32)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC, 64)
+DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, 64)
+DECODE_OPERAND_SREG_7(SReg_96, 96)
+DECODE_OPERAND_SREG_7(SReg_128, 128)
+DECODE_OPERAND_SREG_7(SReg_128_XNULL, 128)
+DECODE_OPERAND_SREG_7(SReg_256, 256)
+DECODE_OPERAND_SREG_7(SReg_256_XNULL, 256)
+DECODE_OPERAND_SREG_7(SReg_512, 512)
+
+DECODE_OPERAND_SREG_8(SReg_64, 64)
DECODE_OPERAND_REG_8(AGPR_32)
DECODE_OPERAND_REG_8(AReg_64)
@@ -311,7 +309,7 @@ DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
@@ -326,7 +324,7 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(OpWidth, Imm & 0xFF));
}
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus
decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm,
uint64_t /*Addr*/,
@@ -342,7 +340,7 @@ decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm,
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(OpWidth, Imm & 0xFF));
}
-template <AMDGPUDisassembler::OpWidthTy OpWidth>
+template <unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
@@ -397,8 +395,7 @@ static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
}
-static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
- AMDGPUDisassembler::OpWidthTy Opw,
+static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, unsigned Opw,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
if (!DAsm->isGFX90A()) {
@@ -432,7 +429,7 @@ static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
}
-template <AMDGPUDisassembler::OpWidthTy Opw>
+template <unsigned Opw>
static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
@@ -444,7 +441,7 @@ static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
const MCDisassembler *Decoder) {
assert(Imm < (1 << 9) && "9-bit encoding");
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
+ return addOperand(Inst, DAsm->decodeSrcOp(64, Imm));
}
#define DECODE_SDWA(DecName) \
@@ -1629,102 +1626,130 @@ static int64_t getInlineImmValBF16(unsigned Imm) {
}
}
-unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
+unsigned AMDGPUDisassembler::getVgprClassId(unsigned Width) const {
using namespace AMDGPU;
- assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
- default: // fall
- case OPW32:
- case OPW16:
- case OPWV216:
+ case 16:
+ case 32:
return VGPR_32RegClassID;
- case OPW64:
- case OPWV232: return VReg_64RegClassID;
- case OPW96: return VReg_96RegClassID;
- case OPW128: return VReg_128RegClassID;
- case OPW192: return VReg_192RegClassID;
- case OPW160: return VReg_160RegClassID;
- case OPW256: return VReg_256RegClassID;
- case OPW288: return VReg_288RegClassID;
- case OPW320: return VReg_320RegClassID;
- case OPW352: return VReg_352RegClassID;
- case OPW384: return VReg_384RegClassID;
- case OPW512: return VReg_512RegClassID;
- case OPW1024: return VReg_1024RegClassID;
- }
-}
-
-unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
+ case 64:
+ return VReg_64RegClassID;
+ case 96:
+ return VReg_96RegClassID;
+ case 128:
+ return VReg_128RegClassID;
+ case 160:
+ return VReg_160RegClassID;
+ case 192:
+ return VReg_192RegClassID;
+ case 256:
+ return VReg_256RegClassID;
+ case 288:
+ return VReg_288RegClassID;
+ case 320:
+ return VReg_320RegClassID;
+ case 352:
+ return VReg_352RegClassID;
+ case 384:
+ return VReg_384RegClassID;
+ case 512:
+ return VReg_512RegClassID;
+ case 1024:
+ return VReg_1024RegClassID;
+ }
+ llvm_unreachable("Invalid register width!");
+}
+
+unsigned AMDGPUDisassembler::getAgprClassId(unsigned Width) const {
using namespace AMDGPU;
- assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
- default: // fall
- case OPW32:
- case OPW16:
- case OPWV216:
+ case 16:
+ case 32:
return AGPR_32RegClassID;
- case OPW64:
- case OPWV232: return AReg_64RegClassID;
- case OPW96: return AReg_96RegClassID;
- case OPW128: return AReg_128RegClassID;
- case OPW160: return AReg_160RegClassID;
- case OPW256: return AReg_256RegClassID;
- case OPW288: return AReg_288RegClassID;
- case OPW320: return AReg_320RegClassID;
- case OPW352: return AReg_352RegClassID;
- case OPW384: return AReg_384RegClassID;
- case OPW512: return AReg_512RegClassID;
- case OPW1024: return AReg_1024RegClassID;
- }
-}
-
-
-unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
+ case 64:
+ return AReg_64RegClassID;
+ case 96:
+ return AReg_96RegClassID;
+ case 128:
+ return AReg_128RegClassID;
+ case 160:
+ return AReg_160RegClassID;
+ case 256:
+ return AReg_256RegClassID;
+ case 288:
+ return AReg_288RegClassID;
+ case 320:
+ return AReg_320RegClassID;
+ case 352:
+ return AReg_352RegClassID;
+ case 384:
+ return AReg_384RegClassID;
+ case 512:
+ return AReg_512RegClassID;
+ case 1024:
+ return AReg_1024RegClassID;
+ }
+ llvm_unreachable("Invalid register width!");
+}
+
+unsigned AMDGPUDisassembler::getSgprClassId(unsigned Width) const {
using namespace AMDGPU;
- assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
- default: // fall
- case OPW32:
- case OPW16:
- case OPWV216:
+ case 16:
+ case 32:
return SGPR_32RegClassID;
- case OPW64:
- case OPWV232: return SGPR_64RegClassID;
- case OPW96: return SGPR_96RegClassID;
- case OPW128: return SGPR_128RegClassID;
- case OPW160: return SGPR_160RegClassID;
- case OPW256: return SGPR_256RegClassID;
- case OPW288: return SGPR_288RegClassID;
- case OPW320: return SGPR_320RegClassID;
- case OPW352: return SGPR_352RegClassID;
- case OPW384: return SGPR_384RegClassID;
- case OPW512: return SGPR_512RegClassID;
- }
-}
-
-unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
+ case 64:
+ return SGPR_64RegClassID;
+ case 96:
+ return SGPR_96RegClassID;
+ case 128:
+ return SGPR_128RegClassID;
+ case 160:
+ return SGPR_160RegClassID;
+ case 256:
+ return SGPR_256RegClassID;
+ case 288:
+ return SGPR_288RegClassID;
+ case 320:
+ return SGPR_320RegClassID;
+ case 352:
+ return SGPR_352RegClassID;
+ case 384:
+ return SGPR_384RegClassID;
+ case 512:
+ return SGPR_512RegClassID;
+ }
+ llvm_unreachable("Invalid register width!");
+}
+
+unsigned AMDGPUDisassembler::getTtmpClassId(unsigned Width) const {
using namespace AMDGPU;
- assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
- default: // fall
- case OPW32:
- case OPW16:
- case OPWV216:
+ case 16:
+ case 32:
return TTMP_32RegClassID;
- case OPW64:
- case OPWV232: return TTMP_64RegClassID;
- case OPW128: return TTMP_128RegClassID;
- case OPW256: return TTMP_256RegClassID;
- case OPW288: return TTMP_288RegClassID;
- case OPW320: return TTMP_320RegClassID;
- case OPW352: return TTMP_352RegClassID;
- case OPW384: return TTMP_384RegClassID;
- case OPW512: return TTMP_512RegClassID;
- }
+ case 64:
+ return TTMP_64RegClassID;
+ case 128:
+ return TTMP_128RegClassID;
+ case 256:
+ return TTMP_256RegClassID;
+ case 288:
+ return TTMP_288RegClassID;
+ case 320:
+ return TTMP_320RegClassID;
+ case 352:
+ return TTMP_352RegClassID;
+ case 384:
+ return TTMP_384RegClassID;
+ case 512:
+ return TTMP_512RegClassID;
+ }
+ llvm_unreachable("Invalid register width!");
}
int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
@@ -1736,8 +1761,7 @@ int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
}
-MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width,
- unsigned Val) const {
+MCOperand AMDGPUDisassembler::decodeSrcOp(unsigned Width, unsigned Val) const {
using namespace AMDGPU::EncValues;
assert(Val < 1024); // enum10
@@ -1752,7 +1776,7 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width,
return decodeNonVGPRSrcOp(Width, Val & 0xFF);
}
-MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width,
+MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(unsigned Width,
unsigned Val) const {
// Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been
// decoded earlier.
@@ -1776,17 +1800,15 @@ MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width,
return MCOperand::createImm(Val);
switch (Width) {
- case OPW32:
- case OPW16:
- case OPWV216:
+ case 32:
+ case 16:
return decodeSpecialReg32(Val);
- case OPW64:
- case OPWV232:
+ case 64:
return decodeSpecialReg64(Val);
- case OPW96:
- case OPW128:
- case OPW256:
- case OPW512:
+ case 96:
+ case 128:
+ case 256:
+ case 512:
return decodeSpecialReg96Plus(Val);
default:
llvm_unreachable("unexpected immediate type");
@@ -1803,8 +1825,7 @@ MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst,
assert(Inst.getOperand(VDstXInd).isReg());
unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
Val |= ~XDstReg & 1;
- auto Width = llvm::AMDGPUDisassembler::OPW32;
- return createRegOperand(getVgprClassId(Width), Val);
+ return createRegOperand(getVgprClassId(32), Val);
}
MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
@@ -1892,7 +1913,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg96Plus(unsigned Val) const {
return errOperand(Val, "unknown operand encoding " + Twine(Val));
}
-MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
+MCOperand AMDGPUDisassembler::decodeSDWASrc(unsigned Width,
const unsigned Val) const {
using namespace AMDGPU::SDWA;
using namespace AMDGPU::EncValues;
@@ -1932,11 +1953,11 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
}
MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
- return decodeSDWASrc(OPW16, Val);
+ return decodeSDWASrc(16, Val);
}
MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
- return decodeSDWASrc(OPW32, Val);
+ return decodeSDWASrc(32, Val);
}
MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
@@ -1953,25 +1974,24 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
int TTmpIdx = getTTmpIdx(Val);
if (TTmpIdx >= 0) {
- auto TTmpClsId = getTtmpClassId(IsWave32 ? OPW32 : OPW64);
+ auto TTmpClsId = getTtmpClassId(IsWave32 ? 32 : 64);
return createSRegOperand(TTmpClsId, TTmpIdx);
}
if (Val > SGPR_MAX) {
return IsWave32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
}
- return createSRegOperand(getSgprClassId(IsWave32 ? OPW32 : OPW64), Val);
+ return createSRegOperand(getSgprClassId(IsWave32 ? 32 : 64), Val);
}
return createRegOperand(IsWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);
}
MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
- return STI.hasFeature(AMDGPU::FeatureWavefrontSize32)
- ? decodeSrcOp(OPW32, Val)
- : decodeSrcOp(OPW64, Val);
+ return STI.hasFeature(AMDGPU::FeatureWavefrontSize32) ? decodeSrcOp(32, Val)
+ : decodeSrcOp(64, Val);
}
MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const {
- return decodeSrcOp(OPW32, Val);
+ return decodeSrcOp(32, Val);
}
MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const {
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 4603e8587a3a0..3ca7c3e1fd682 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -186,47 +186,26 @@ class AMDGPUDisassembler : public MCDisassembler {
void convertMacDPPInst(MCInst &MI) const;
void convertTrue16OpSel(MCInst &MI) const;
- enum OpWidthTy {
- OPW32,
- OPW64,
- OPW96,
- OPW128,
- OPW160,
- OPW192,
- OPW256,
- OPW288,
- OPW320,
- OPW352,
- OPW384,
- OPW512,
- OPW1024,
- OPW16,
- OPWV216,
- OPWV232,
- OPW_LAST_,
- OPW_FIRST_ = OPW32
- };
-
- unsigned getVgprClassId(const OpWidthTy Width) const;
- unsigned getAgprClassId(const OpWidthTy Width) const;
- unsigned getSgprClassId(const OpWidthTy Width) const;
- unsigned getTtmpClassId(const OpWidthTy Width) const;
+ unsigned getVgprClassId(unsigned Width) const;
+ unsigned getAgprClassId(unsigned Width) const;
+ unsigned getSgprClassId(unsigned Width) const;
+ unsigned getTtmpClassId(unsigned Width) const;
static MCOperand decodeIntImmed(unsigned Imm);
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
MCOperand decodeLiteralConstant(bool ExtendFP64) const;
- MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
+ MCOperand decodeSrcOp(unsigned Width, unsigned Val) const;
- MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val) const;
+ MCOperand decodeNonVGPRSrcOp(unsigned Width, unsigned Val) const;
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
MCOperand decodeSpecialReg32(unsigned Val) const;
MCOperand decodeSpecialReg64(unsigned Val) const;
MCOperand decodeSpecialReg96Plus(unsigned Val) const;
- MCOperand decodeSDWASrc(const OpWidthTy Width, unsign...
[truncated]
|
kosarev
commented
May 8, 2025
| @@ -1629,102 +1626,130 @@ static int64_t getInlineImmValBF16(unsigned Imm) { | |||
| } | |||
| } | |||
|
|
|||
| unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { | |||
| unsigned AMDGPUDisassembler::getVgprClassId(unsigned Width) const { | |||
There was a problem hiding this comment.
We have such functions elsewhere, so might be possible to combine them.
There was a problem hiding this comment.
That would be great! There are far too many tables that need updating when you add support for a new register width.
There was a problem hiding this comment.
Just in case: I'm not planning combining them in this patch.
This erases the distinction between OPWV216 and OPW32, so I guess nothing actually depended on that distinction? |
What |
arsenm
reviewed
May 8, 2025
arsenm
approved these changes
May 8, 2025
Yes, in progress. |
lenary
added a commit
to lenary/llvm-project
that referenced
this pull request
May 9, 2025
* main: (420 commits) [AArch64] Merge scaled and unscaled narrow zero stores (llvm#136705) [RISCV] One last migration to getInsertSubvector [nfc] [flang][OpenMP] Update `do concurrent` mapping pass to use `fir.do_concurrent` op (llvm#138489) [MLIR][LLVM] Fix llvm.mlir.global mismatching print and parser order (llvm#138986) [lld][NFC] Fix minor typo in docs (llvm#138898) [RISCV] Migrate getConstant indexed insert/extract subvector to new API (llvm#139111) GlobalISel: Translate minimumnum and maximumnum (llvm#139106) [MemProf] Simplify unittest save and restore of options (llvm#139117) [BOLT][AArch64] Patch functions targeted by optional relocs (llvm#138750) [Coverage] Support -fprofile-list for cold function coverage (llvm#136333) Remove unused forward decl (llvm#139108) [AMDGPU][NFC] Get rid of OPW constants. (llvm#139074) [CIR] Upstream extract op for VectorType (llvm#138413) [mlir][xegpu] Handle scalar uniform ops in SIMT distribution. (llvm#138593) [GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (llvm#138574) AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (llvm#128911) Reland [Clang] Deprecate `__is_trivially_relocatable` (llvm#139061) [HLSL][NFC] Stricter Overload Tests (clamp,max,min,pow) (llvm#138993) [MLIR] Fixing the memref linearization size computation for non-packed memref (llvm#138922) [TableGen][NFC] Use early exit to simplify large block in emitAction. (llvm#138220) ...
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We can infer the widths from register classes and represent them as numbers.