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[SelectionDAG] Handle fneg/fabs/fcopysign in SimplifyDemandedBits #139239

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[SelectionDAG] Handle fneg/fabs/fcopysign in SimplifyDemandedBits #139239

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[SelectionDAG] Handle `fneg`/`fabs`/`fcopysign` in `SimplifyDemandedB…
el-ev May 9, 2025
61c772f
update
el-ev May 10, 2025
5e5fb4c
Merge branch 'main' into users/el-ev/populate-simplify-demanded-bits
el-ev May 10, 2025
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29 changes: 6 additions & 23 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -18259,21 +18259,6 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
}
}

// copysign(fabs(x), y) -> copysign(x, y)
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I think it may help if we can observe test changes with the SimplifyDemandedBits changes alone, without dropping the existing combines

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I've tested locally, nothing changes when adding the removed combines back. But regressions happen when fold (fabs (fabs x)) -> (fabs x) at L18878-L18880 is removed.

// copysign(fneg(x), y) -> copysign(x, y)
// copysign(copysign(x,z), y) -> copysign(x, y)
if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
N0.getOpcode() == ISD::FCOPYSIGN)
return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0.getOperand(0), N1);

// copysign(x, abs(y)) -> abs(x)
if (N1.getOpcode() == ISD::FABS)
return DAG.getNode(ISD::FABS, DL, VT, N0);

// copysign(x, copysign(y,z)) -> copysign(x, z)
if (N1.getOpcode() == ISD::FCOPYSIGN)
return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0, N1.getOperand(1));

// copysign(x, fp_extend(y)) -> copysign(x, y)
// copysign(x, fp_round(y)) -> copysign(x, y)
if (CanCombineFCOPYSIGN_EXTEND_ROUND(N))
Expand Down Expand Up @@ -18814,6 +18799,9 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
N0.getOperand(0));
}

if (SimplifyDemandedBits(N0, APInt::getAllOnes(VT.getScalarSizeInBits())))
return SDValue(N, 0);

if (SDValue Cast = foldSignChangeInBitcast(N))
return Cast;

Expand Down Expand Up @@ -18887,14 +18875,9 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FABS, DL, VT, {N0}))
return C;

// fold (fabs (fabs x)) -> (fabs x)
if (N0.getOpcode() == ISD::FABS)
return N->getOperand(0);

// fold (fabs (fneg x)) -> (fabs x)
// fold (fabs (fcopysign x, y)) -> (fabs x)
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
return DAG.getNode(ISD::FABS, DL, VT, N0.getOperand(0));
if (SimplifyDemandedBits(N0,
APInt::getSignedMaxValue(VT.getScalarSizeInBits())))
return SDValue(N, 0);

if (SDValue Cast = foldSignChangeInBitcast(N))
return Cast;
Expand Down
71 changes: 71 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -2958,6 +2958,77 @@ bool TargetLowering::SimplifyDemandedBits(
}
break;
}
case ISD::FABS: {
SDValue Op0 = Op.getOperand(0);
APInt SignMask = APInt::getSignMask(BitWidth);

if (!DemandedBits.intersects(SignMask))
return TLO.CombineTo(Op, Op0);

if (SimplifyDemandedBits(Op0, ~SignMask & DemandedBits, DemandedElts, Known,
TLO, Depth + 1))
return true;

if (Known.isNonNegative())
return TLO.CombineTo(Op, Op0);
if (Known.isNegative())
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::FNEG, dl, VT, Op0));

Known.Zero |= SignMask;
Known.One &= ~SignMask;

break;
}
case ISD::FCOPYSIGN: {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
APInt SignMask = APInt::getSignMask(BitWidth);

if (!DemandedBits.intersects(SignMask))
return TLO.CombineTo(Op, Op0);

if (SimplifyDemandedBits(Op0, ~SignMask & DemandedBits, DemandedElts, Known,
TLO, Depth + 1))
return true;
if (SimplifyDemandedBits(Op1, SignMask, DemandedElts, Known2, TLO,
Depth + 1))
return true;

if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
return true;

if ((Known.isNonNegative() && Known2.isNonNegative()) ||
(Known.isNegative() && Known2.isNegative()))
return TLO.CombineTo(Op, Op0);

if (Known2.isNonNegative())
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::FABS, dl, VT, Op0));

if (Known2.isNegative()) {
Known.One |= SignMask;
Known.Zero &= ~SignMask;
}

break;
}
case ISD::FNEG: {
SDValue Op0 = Op.getOperand(0);
APInt SignMask = APInt::getSignMask(BitWidth);

if (!DemandedBits.intersects(SignMask))
return TLO.CombineTo(Op, Op0);

if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known, TLO,
Depth + 1))
return true;

if (Known.isNonNegative() || Known.isNegative()) {
Known.Zero ^= SignMask;
Known.One ^= SignMask;
}

break;
}
default:
// We also ask the target about intrinsics (which could be specific to it).
if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/AArch64/extract-vector-elt.ll
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Expand Up @@ -425,10 +425,7 @@ entry:
define float @extract_v4i32_copysign_build_vector_const(<4 x float> %a, <4 x float> %b, i32 %c) {
; CHECK-SD-LABEL: extract_v4i32_copysign_build_vector_const:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: adrp x8, .LCPI17_0
; CHECK-SD-NEXT: mvni v1.4s, #128, lsl #24
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI17_0]
; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b
; CHECK-SD-NEXT: fabs v0.4s, v0.4s
; CHECK-SD-NEXT: mov s0, v0.s[2]
; CHECK-SD-NEXT: ret
;
Expand Down
38 changes: 21 additions & 17 deletions llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
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Expand Up @@ -427,16 +427,18 @@ entry:
define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-942: ; %bb.0: ; %entry
; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-942-NEXT: v_cvt_f32_f64_e64 v8, |v[0:1]|
; GFX-942-NEXT: v_and_b32_e32 v5, 0x7fffffff, v1
; GFX-942-NEXT: v_mov_b32_e32 v4, v0
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
; GFX-942-NEXT: v_and_b32_e32 v9, 1, v8
; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[4:5]|, |v[6:7]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[6:7]
; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: v_add_u32_e32 v4, v8, v4
; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
Expand All @@ -449,16 +451,18 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
;
; GFX-950-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-950: ; %bb.0: ; %entry
; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: v_cvt_f32_f64_e64 v8, |v[0:1]|
; GFX-950-NEXT: v_and_b32_e32 v5, 0x7fffffff, v1
; GFX-950-NEXT: v_mov_b32_e32 v4, v0
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[6:7]
; GFX-950-NEXT: v_and_b32_e32 v0, 1, v8
; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[4:5]|, |v[6:7]|
; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v8, v0
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AMDGPU/bf16.ll
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Expand Up @@ -18639,17 +18639,17 @@ define bfloat @v_fabs_bf16(bfloat %a) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
Comment on lines +18642 to +18643
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Kind of a regression? It should be neutral in code size and cycles, but probably should prefer a bit-op to an FP op (e.g. this avoids the mode dependency)

; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -18832,8 +18832,8 @@ define bfloat @v_fneg_fabs_bf16(bfloat %a) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
Expand All @@ -18843,8 +18843,8 @@ define bfloat @v_fneg_fabs_bf16(bfloat %a) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
Expand Down Expand Up @@ -18889,23 +18889,23 @@ define amdgpu_ps i32 @s_fneg_fabs_bf16(bfloat inreg %a) {
; GCN-LABEL: s_fneg_fabs_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, s0
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_bitset0_b32 s0, 31
; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
; GCN-NEXT: s_xor_b32 s0, s0, 0x80000000
; GCN-NEXT: s_lshr_b32 s0, s0, 16
; GCN-NEXT: ; return to shader part epilog
;
; GFX7-LABEL: s_fneg_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, s0
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, |v0|
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
; GFX7-NEXT: s_bitset0_b32 s0, 31
; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
; GFX7-NEXT: s_xor_b32 s0, s0, 0x80000000
; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fneg_fabs_bf16:
Expand Down
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