[BOLT] [PowerPC] Port

bolt/CMakeLists.txt

@@ -58,7 +58,7 @@ endif() # standalone
 
 # Determine default set of targets to build -- the intersection of
 # those BOLT supports and those LLVM is targeting.
-set(BOLT_TARGETS_TO_BUILD_all "AArch64;X86;RISCV")
+set(BOLT_TARGETS_TO_BUILD_all "AArch64;X86;RISCV;PowerPC")
 set(BOLT_TARGETS_TO_BUILD_default)
 foreach (tgt ${BOLT_TARGETS_TO_BUILD_all})
   if (tgt IN_LIST LLVM_TARGETS_TO_BUILD)

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -2293,6 +2293,11 @@ MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *,
                                         const MCRegisterInfo *,
                                         const MCSubtargetInfo *);
 
+MCPlusBuilder *createPowerPCMCPlusBuilder(const MCInstrAnalysis *,
+                                          const MCInstrInfo *,
+                                          const MCRegisterInfo *,
+                                          const MCSubtargetInfo *);
+
 } // namespace bolt
 } // namespace llvm
 

bolt/lib/Rewrite/RewriteInstance.cpp

@@ -304,6 +304,11 @@ MCPlusBuilder *createMCPlusBuilder(const Triple::ArchType Arch,
     return createRISCVMCPlusBuilder(Analysis, Info, RegInfo, STI);
 #endif
 
+#ifdef POWERPC_AVAILABLE
+  if (Arch == Triple::ppc64 || Arch == Triple::ppc64le)
+    return createPowerPCMCPlusBuilder(Analysis, Info, RegInfo, STI);
+#endif
+
   llvm_unreachable("architecture unsupported by MCPlusBuilder");
 }
 

bolt/lib/Target/CMakeLists.txt

@@ -1,3 +1,5 @@
 foreach (tgt ${BOLT_TARGETS_TO_BUILD})
   add_subdirectory(${tgt})
-endforeach()
+  string(TOUPPER ${tgt} TGT_UPPER)
+  add_definitions(-D${TGT_UPPER}_AVAILABLE)
+endforeach()

bolt/lib/Target/PowerPC/CMakeLists.txt

@@ -0,0 +1,29 @@
+add_llvm_library(LLVMBOLTTargetPowerPC
+    PPCMCPlusBuilder.cpp
+)
+
+target_include_directories(LLVMBOLTTargetPowerPC PRIVATE
+    ${LLVM_BINARY_DIR}/include
+    ${LLVM_SOURCE_DIR}/include
+)
+
+file(MAKE_DIRECTORY "${LLVM_BINARY_DIR}/include/llvm/Target/PowerPC")
+
+foreach(incfile IN ITEMS
+    PPCGenInstrInfo.inc
+    PPCGenRegisterInfo.inc
+)
+    add_custom_command(
+        OUTPUT "${LLVM_BINARY_DIR}/include/llvm/Target/PowerPC/${incfile}"
+        COMMAND ${CMAKE_COMMAND} -E copy_if_different
+            "${LLVM_BINARY_DIR}/lib/Target/PowerPC/${incfile}"
+            "${LLVM_BINARY_DIR}/include/llvm/Target/PowerPC/${incfile}"
+        DEPENDS "${LLVM_BINARY_DIR}/lib/Target/PowerPC/${incfile}"
+        COMMENT "Copying ${incfile} to include directory"
+    )
+    add_custom_target(
+        "BoltCopy${incfile}" ALL
+        DEPENDS "${LLVM_BINARY_DIR}/include/llvm/Target/PowerPC/${incfile}"
+    )
+    add_dependencies(LLVMBOLTTargetPowerPC "BoltCopy${incfile}")
+endforeach()

bolt/lib/Target/PowerPC/PPCMCPlusBuilder.cpp

@@ -0,0 +1,54 @@
+//===- bolt/Target/PowerPC/PPCMCPlusBuilder.cpp -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides PowerPC-specific MCPlus builder.
+//
+//===----------------------------------------------------------------------===//
+
+#include "bolt/Core/MCPlusBuilder.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#define GET_INSTRINFO_ENUM
+#include "llvm/Target/PowerPC/PPCGenInstrInfo.inc"
+#define GET_REGINFO_ENUM
+#include "llvm/Target/PowerPC/PPCGenRegisterInfo.inc"
+
+namespace llvm {
+namespace bolt {
+
+class PPCMCPlusBuilder : public MCPlusBuilder {
+public:
+  using MCPlusBuilder::MCPlusBuilder;
+
+  // Create instructions to push two registers onto the stack
+  static void createPushRegisters(MCInst &Inst1, MCInst &Inst2, MCPhysReg Reg1,
+                                  MCPhysReg /*Reg2*/) {
+
+    Inst1.clear();
+    Inst1.setOpcode(PPC::STDU);
+    Inst1.addOperand(MCOperand::createReg(PPC::R1)); // destination (SP)
+    Inst1.addOperand(MCOperand::createReg(PPC::R1)); // base (SP)
+    Inst1.addOperand(MCOperand::createImm(-16));     // offset
+
+    Inst2.clear();
+    Inst2.setOpcode(PPC::STD);
+    Inst2.addOperand(MCOperand::createReg(Reg1));    // source register
+    Inst2.addOperand(MCOperand::createReg(PPC::R1)); // base (SP)
+    Inst2.addOperand(MCOperand::createImm(0));       // offset
+  }
+};
+
+MCPlusBuilder *createPowerPCMCPlusBuilder(const MCInstrAnalysis *Analysis,
+                                          const MCInstrInfo *Info,
+                                          const MCRegisterInfo *RegInfo,
+                                          const MCSubtargetInfo *STI) {
+  return new PPCMCPlusBuilder(Analysis, Info, RegInfo, STI);
+}
+
+} // namespace bolt
+} // namespace llvm