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[mlir][LLVM] Model side effects of volatile and atomic load-store #65730

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Merged
merged 3 commits into from
Sep 8, 2023
Merged

[mlir][LLVM] Model side effects of volatile and atomic load-store #65730

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d32d6c5
[mlir][LLVM] Model side effects of volatile and atomic load-store
zero9178 Sep 8, 2023
4b554ee
Merge branch 'main' into volatile-side-effects
zero9178 Sep 8, 2023
8e056d5
address review comments
zero9178 Sep 8, 2023
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10 changes: 6 additions & 4 deletions mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -326,9 +326,10 @@ def LLVM_GEPOp : LLVM_Op<"getelementptr", [Pure,
}

def LLVM_LoadOp : LLVM_MemAccessOpBase<"load",
[DeclareOpInterfaceMethods<PromotableMemOpInterface>,
[DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
DeclareOpInterfaceMethods<PromotableMemOpInterface>,
DeclareOpInterfaceMethods<SafeMemorySlotAccessOpInterface>]> {
dag args = (ins Arg<LLVM_PointerTo<LLVM_LoadableType>, "", [MemRead]>:$addr,
dag args = (ins LLVM_PointerTo<LLVM_LoadableType>:$addr,
OptionalAttr<I64Attr>:$alignment,
UnitAttr:$volatile_,
UnitAttr:$nontemporal,
Expand Down Expand Up @@ -399,10 +400,11 @@ def LLVM_LoadOp : LLVM_MemAccessOpBase<"load",
}

def LLVM_StoreOp : LLVM_MemAccessOpBase<"store",
[DeclareOpInterfaceMethods<PromotableMemOpInterface>,
[DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
DeclareOpInterfaceMethods<PromotableMemOpInterface>,
DeclareOpInterfaceMethods<SafeMemorySlotAccessOpInterface>]> {
dag args = (ins LLVM_LoadableType:$value,
Arg<LLVM_PointerTo<LLVM_LoadableType>,"",[MemWrite]>:$addr,
LLVM_PointerTo<LLVM_LoadableType>:$addr,
OptionalAttr<I64Attr>:$alignment,
UnitAttr:$volatile_,
UnitAttr:$nontemporal,
Expand Down
22 changes: 22 additions & 0 deletions mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -812,6 +812,17 @@ Type GEPOp::getResultPtrElementType() {
// LoadOp
//===----------------------------------------------------------------------===//

void LoadOp::getEffects(
SmallVectorImpl<SideEffects::EffectInstance<MemoryEffects::Effect>>
&effects) {
effects.emplace_back(MemoryEffects::Read::get(), getAddr());
if (getVolatile_() || (getOrdering() != AtomicOrdering::not_atomic &&
getOrdering() != AtomicOrdering::unordered)) {
effects.emplace_back(MemoryEffects::Write::get());
effects.emplace_back(MemoryEffects::Read::get());
}
}

/// Returns true if the given type is supported by atomic operations. All
/// integer and float types with limited bit width are supported. Additionally,
/// depending on the operation pointers may be supported as well.
Expand Down Expand Up @@ -932,6 +943,17 @@ static void printLoadType(OpAsmPrinter &printer, Operation *op, Type type,
// StoreOp
//===----------------------------------------------------------------------===//

void StoreOp::getEffects(
SmallVectorImpl<SideEffects::EffectInstance<MemoryEffects::Effect>>
&effects) {
effects.emplace_back(MemoryEffects::Write::get(), getAddr());
if (getVolatile_() || (getOrdering() != AtomicOrdering::not_atomic &&
getOrdering() != AtomicOrdering::unordered)) {
effects.emplace_back(MemoryEffects::Write::get());
effects.emplace_back(MemoryEffects::Read::get());
}
}

LogicalResult StoreOp::verify() {
Type valueType = getValue().getType();
return verifyAtomicMemOp(*this, valueType,
Expand Down
17 changes: 17 additions & 0 deletions mlir/test/Dialect/LLVMIR/canonicalize.mlir
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Expand Up @@ -191,3 +191,20 @@ llvm.func @alloca_dce() {
%0 = llvm.alloca %c1_i64 x i32 : (i64) -> !llvm.ptr
llvm.return
}

// -----

// CHECK-LABEL: func @volatile_load
llvm.func @volatile_load(%x : !llvm.ptr) {
// A volatile load may have side-effects such as a write operation to arbitrary memory.
// Make sure it is not removed.
// CHECK: llvm.load volatile
%0 = llvm.load volatile %x : !llvm.ptr -> i8
// Same with monotonic atomics and any stricter modes.
// CHECK: llvm.load %{{.*}} atomic monotonic
%2 = llvm.load %x atomic monotonic { alignment = 1 } : !llvm.ptr -> i8
// But not unordered!
// CHECK-NOT: llvm.load %{{.*}} atomic unordered
%3 = llvm.load %x atomic unordered { alignment = 1 } : !llvm.ptr -> i8
llvm.return
}