Skip to content

[Sparc] Remove LEA instructions (NFCI) #65850

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 20, 2023
Merged

[Sparc] Remove LEA instructions (NFCI) #65850

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,7 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,

static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
MI.addOperand(MCOperand::createImm(tgt));
assert(isUInt<13>(insn));
MI.addOperand(MCOperand::createImm(SignExtend64<13>(insn)));
return MCDisassembler::Success;
}
10 changes: 1 addition & 9 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -148,15 +148,7 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,

void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
printOperand(MI, opNum, STI, O);
O << ", ";
printOperand(MI, opNum + 1, STI, O);
return;
}

raw_ostream &O) {
const MCOperand &Op1 = MI->getOperand(opNum);
const MCOperand &Op2 = MI->getOperand(opNum + 1);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ class SparcInstPrinter : public MCInstPrinter {
void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
raw_ostream &OS);
void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
raw_ostream &OS, const char *Modifier = nullptr);
raw_ostream &OS);
void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
raw_ostream &OS);
bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/Sparc/SparcInstr64Bit.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -171,12 +171,6 @@ def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
"add $rs1, $rs2, $rd, $sym",
[(set i64:$rd,
(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;

// "LEA" form of add
def LEAX_ADDri : F3_2<2, 0b000000,
(outs I64Regs:$rd), (ins (MEMri $rs1, $simm13):$addr),
"add ${addr:arith}, $rd",
[(set iPTR:$rd, ADDRri:$addr)]>;
}

def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
Expand Down
38 changes: 19 additions & 19 deletions llvm/lib/Target/Sparc/SparcInstrAliases.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -486,41 +486,41 @@ let Predicates = [HasV9] in {
def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;

// inc simm13, rd -> add rd, simm13, rd
def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// inccc rd -> addcc rd, 1, rd
def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;

// inccc simm13, rd -> addcc rd, simm13, rd
def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// dec rd -> sub rd, 1, rd
def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;

// dec simm13, rd -> sub rd, simm13, rd
def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// deccc rd -> subcc rd, 1, rd
def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;

// deccc simm13, rd -> subcc rd, simm13, rd
def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, simm13Op:$simm13), 0>;

// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;

// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;


// clr rd -> or %g0, %g0, rd
Expand All @@ -537,7 +537,7 @@ def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;

// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, simm13Op:$simm13)>;

// mov specialreg, rd -> rd specialreg, rd
def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
Expand All @@ -547,13 +547,13 @@ def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;

// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;

// End of Section A.3

Expand All @@ -566,23 +566,23 @@ let EmitPriority = 0 in
// (aka: omit the first arg when it's g0. This is not in the manual, but is
// supported by gnu and solaris as)
def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;

def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, simm13Op:$simm13), 0>;

// wrpr %reg, %rd -> wrpr %reg, %g0, %rd
// wrpr imm, %rd -> wrpr %g0, imm, %rd
// Nonstandard GNU extensions.
let Predicates = [HasV9] in {
def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, i32imm:$simm13), 0>;
def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, simm13Op:$simm13), 0>;
}

// flush -> flush %g0
Expand Down
17 changes: 8 additions & 9 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,7 @@ def SETHIimm_not : PatLeaf<(i32 imm), [{

// Addressing modes.
def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [], []>;

// Constrained operands for the shift operations.
class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass {
Expand Down Expand Up @@ -221,7 +221,7 @@ def calltarget : Operand<i32> {
let ParserMatchClass = SparcCallTargetAsmOperand;
}

def simm13Op : Operand<i32> {
def simm13Op : Operand<iPTR> {
let DecoderMethod = "DecodeSIMM13";
let EncoderMethod = "getSImm13OpValue";
}
Expand Down Expand Up @@ -815,13 +815,6 @@ defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>;
// Section B.13 - Add Instructions, p. 108
defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;

// "LEA" forms of add (patterns to make tblgen happy)
let Predicates = [Is32Bit], isCodeGenOnly = 1 in
def LEA_ADDri : F3_2<2, 0b000000,
(outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
"add ${addr:arith}, $rd",
[(set iPTR:$rd, ADDRri:$addr)]>;

let Defs = [ICC] in
defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;

Expand Down Expand Up @@ -1831,6 +1824,12 @@ def : Pat<(i32 simm13:$val),
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;

// Frame index.
def to_tframeindex : SDNodeXForm<frameindex, [{
return CurDAG->getTargetFrameIndex(N->getIndex(), N->getValueType(0));
}]>;
def : Pat<(i32 (frameindex:$ptr)), (ADDri (i32 (to_tframeindex $ptr)), (i32 0))>;
def : Pat<(i64 (frameindex:$ptr)), (ADDri (i64 (to_tframeindex $ptr)), (i64 0))>;

// Global addresses, constant pool entries
let Predicates = [Is32Bit] in {
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/SPARC/fp128-split.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,8 @@ define fp128 @testcase(fp128 %0) {
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:qfpregs = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_odd64
; CHECK: [[LEAX_ADDri:%[0-9]+]]:i64regs = LEAX_ADDri %stack.0, 0
; CHECK: [[ORXri:%[0-9]+]]:i64regs = ORXri killed [[LEAX_ADDri]], 8
; CHECK: [[ADDri:%[0-9]+]]:i64regs = ADDri %stack.0, 0
; CHECK: [[ORXri:%[0-9]+]]:i64regs = ORXri killed [[ADDri]], 8
; CHECK: STDFrr [[ORXri]], $g0, killed [[COPY1]] :: (store (s64) into %stack.0 + 8)
; CHECK: [[COPY2:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_even64
; CHECK: STDFri %stack.0, 0, killed [[COPY2]] :: (store (s64) into %stack.0, align 16)
Expand All @@ -32,8 +32,8 @@ define fp128 @testcase(fp128 %0) {
; CHECK: [[COPY7:%[0-9]+]]:i64regs = COPY [[ADDEri]]
; CHECK: [[SLLXri:%[0-9]+]]:i64regs = SLLXri killed [[COPY7]], 32
; CHECK: [[ORXrr:%[0-9]+]]:i64regs = ORXrr killed [[SLLXri]], killed [[SRLri]]
; CHECK: [[LEAX_ADDri1:%[0-9]+]]:i64regs = LEAX_ADDri %stack.1, 0
; CHECK: [[ORXri1:%[0-9]+]]:i64regs = ORXri killed [[LEAX_ADDri1]], 8
; CHECK: [[ADDri1:%[0-9]+]]:i64regs = ADDri %stack.1, 0
; CHECK: [[ORXri1:%[0-9]+]]:i64regs = ORXri killed [[ADDri1]], 8
; CHECK: STXrr [[ORXri1]], $g0, killed [[ORXrr]] :: (store (s64) into %stack.1 + 8, basealign 16)
; CHECK: [[SRLri1:%[0-9]+]]:i64regs = SRLri killed [[ADDEri1]], 0
; CHECK: [[COPY8:%[0-9]+]]:i64regs = COPY [[ADDEri2]]
Expand Down